EXOSTIV™ Dashboard software (Win 32/64 & Linux) provides the tools to insert EXOSTIV™ IP into the target FPGA and analyze trace data captured from FPGA at runtime.
EXOSTIV™ Dashboard is composed of the Core Inserter and the Analyzer.
EXOSTIV™ Core Inserter is used to set up EXOSTIV IP and synthesize it with the help of the FPGA vendor tool. EXOSTIV™ IP is inserted into the target design at RTL or at netlist level.
In the netlist flow, EXOSTIV™ Core Inserter establishes a communication with the FPGA vendor tool. This enables the extraction of the hierarchy, nodes and clocks, from the target FPGA database. Once EXOSTIV™ IP resources and connections with the target FPGA nodes are defined, the Core Inserter adds EXOSTIV™ IP to the target FPGA design and requests the FPGA vendor tool to run implementation (place & route).
In the RTL flow, EXOSTIV™ Core Inserter uses the FPGA vendor tool to configure the parameters and resources of EXOSTIV™ IP and synthesize it, together with pinout & timing constraints, as well as RTL-level instantiation template.
Once the instrumented FPGA programming file is available and loaded into the target FPGA, EXOSTIV™ Analyzer can use EXOSTIV™ IP to capture data from the target FPGA and upload it to the PC for visualization (MYRIAD™ waveform viewer) and analysis.