FPGA Debug Reloaded.

Getting Started

Getting Started with EXOSTIV™

Getting started with EXOSTIV Dashboard? Here are the steps you’ll need to go through to use EXOSTIV Dashboard.
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EXOSTIV™ for Xilinx, Netlist Flow
EXOSTIV™ for Xilinx or Intel, RTL flow

EXOSTIV™ for Xilinx, Netlist flow

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1. Load Synthesized design into Xilinx Vivado...

2. Start EXOSTIV Dashboard...

3. Establish a link between Vivado and EXOSTIV Dashboard...

4. Use EXOSTIV Core Inserter to set up EXOSTIV IP...

5. Use EXOSTIV Core Inserter to synthesize EXOSTIV IP, insert it into the target design, run implementation and generate the target FPGA bitstream...

6. Load target FPGA with the generated bitstream...

7. Connect EXOSTIV Probe to the target FPGA board and start using EXOSTIV Analyzer...

EXOSTIV™ for Xilinx or Intel, RTL Flow

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Section under construction – thank you for your patience…

1. Start EXOSTIV Dashboard...

2. Use EXOSTIV core inserter to set up and generate EXOSTIV IP

3. Use the generated files to manually instantiate EXOSTIV IP in your source RTL code

4. Use FPGA vendor tool to synthesize, place & route and generate instrumented design programming file

5. Load target FPGA with the generated bitstream...

6. Connect EXOSTIV Probe to the target FPGA board and start using EXOSTIV Analyzer...

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