Exostiv Blade - Managing multiple sites, targets & users In this video, we demonstrate that Exostiv Blade lets you manage multiple sites, target boards and users to reach your FPGA debug, verification and test goals. In a previous demonstration, we already showed that Exostiv Blade core capabilities
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Record FPGA data during 1 hour - really. As ASIC, SoC and FPGA engineers, we are used to watching the operation of our designs based on single limited snapshots. RTL simulations, for instance, provide bit-level details during execution times that span over a few (milli)seconds at best.
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Exostiv - Part 3 - Analyzer Demonstration This is the third and last part of a series of 3 posts that present our flagship product, Exostiv. This is the material that I use as an introduction to Exostiv; it is composed of 3 parts: - Part 1:
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Massive Real-time FPGA Data Capture A game-changer to prevent bug escapes to production. Welcome to this recorded session - thank you for your interest. If you are using AMD Ultrascale™(+) devices then you will be fully aware of the complexity of the designs these FPGAs can hold
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Our new waveform viewer is 10x faster! I am happy to announce that Exostiv Dashboard 1.10.0 has been released this week. In addition to the usual maintenance on supporting new devices, new versions of FPGA tools, and a discreet yet fresh icon set update, this is the
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The FPGA Prototyping problem we are trying to solve 'A la Carte Menu' or 'Full Course Dinner'? Today, choosing a FPGA-based prototyping platform for ASIC or SoC design reduces to 2 choices: - Either you buy or build a FPGA board and choose EDA tools separately; or:
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On-Demand Webinar: 'How to capture Gigabytes of traces from FPGA. At speed.' In this post, you have the opportunity to catch up with our Webinar that ran live earlier this year. In this -now 'on-demand'- webinar we introduce and demonstrate EXOSTIV and show how it can boost
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EXOSTIV lets you peer deeper into FPGA Watch now... EXOSTIV Introduction EXOSTIV's structure (see below) allows deeper data capture from inside FPGA: unlike JTAG instrumentation, EXOSTIV provides an external storage that extends beyond the memory available in the FPGA. Coupled with the usage of transceivers, it creates
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Exostiv provides Gigabytes of visibility into the FPGA running at speed of operation from virtually any board. In this webinar, we'll introduce and demonstrate Exostiv and show how it can boost productivity when designing, debugging and verifying FPGA - and this, whether you use FPGA for ASIC
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Exostiv provides Gigabytes of visibility into the FPGA running at speed of operation from virtually any board. In this webinar, we'll introduce and demonstrate Exostiv and show how it can boost productivity when designing, debugging and verifying FPGA - and this, whether you use FPGA for ASIC
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Record 8GB from a running FPGA - really. In this blog post, I demonstrate 2 different - and extreme? - capture scenarios made possible with EXOSTIV. In the 2 cases, I have used a VCU108 Virtex Ultrascale development kit from Xilinx. (see Xilinx'coverage of EXOSTIV in the
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Deep Trace & Bandwidth Exostiv provides the following maximum capabilities for capturing data from inside FPGA running at speed: Capabilities. 50 Gigabit per second bandwidth for collecting FPGA traces. 8 Gigabyte of memory for trace storage. 32,768 nodes probing simultaneously. 524,288 nodes reach. Actually, we have built
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Debug with reduced footprint Footprint, 'real estate', resources, ... No matter the design complexity, allocating resources to debugging is something you'll worry about. If you are reading these lines, it is likely that you have some interest in running some of your system debugging from a real
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