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Exostiv V1

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Category - Exostiv v1

Exostiv Dashboard Core Inserter
Can I use transceivers located in separate quads for the same IP instance?
Microchip FPGA: which files are produced in RTL flow and how do I use them?
Intel FPGA: which files are produced in RTL flow and how do I use them?
AMD FPGA: which files are produced in RTL flow and how do I use them?
Issue when using Vivado 2020.2
How much FPGA resources does Exostiv IP consume?
In netlist insertion mode, how are nets preserved so they can be probed and not removed during logic optimization?
What is the 'event counter' and how do I use it?
Exostiv Dashboard Tcl commands list
Can I call Exostiv Dashboard from Vivado?
Can I start Exostiv Dashboard in console mode (TCL)?
What is the software build number and how can I check it?
What is 'Number of pipes' in the Capture Configuration of EXOSTIV IP?
Can I run Vivado and Exostiv Dashboard on separate machines for netlist core insertion?
How to use the timing constraints generated by Exostiv Dashboard for Intel?
'Failed to assign pinout' error
Using 'Design Checkpoint' (DCP) flow type
I need a very specific trigger condition. What can I do?
Can I share transceiver resources between EXOSTIV IP and the design?
How do I remove EXOSTIV IP from my netlist to restart insertion?
How can I easily wire my IP throughout hierarchy in RTL flow?
I cannot insert EXOSTIV IP because there is an existing instance with the same name in the target design
What is 'Storage Qualification'?
What is the 'Vivado link timeout' setting?
Can I use a single EXOSTIV Probe with multiple FPGA devices?
Can I probe multiple clock domains?
Can I use Synplify instead of the FPGA vendor synthesis tool?
How many FPGA nodes can I connect to EXOSTIV IP?
Which frequencies are supported for the transceivers reference clock?
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Exostiv IP in Exostiv Dashboard
Can I use transceivers located in separate quads for the same IP instance?
What is the ‘User Register’ and how do I use it?
Microchip FPGA: which files are produced in RTL flow and how do I use them?
Intel FPGA: which files are produced in RTL flow and how do I use them?
AMD FPGA: which files are produced in RTL flow and how do I use them?
Issue when using Vivado 2020.2
How much FPGA resources does Exostiv IP consume?
In netlist insertion mode, how are nets preserved so they can be probed and not removed during logic optimization?
Can I rename the probed signals?
What is the 'event counter' and how do I use it?
How do I send a cross-capture unit trigger?
What is 'Number of pipes' in the Capture Configuration of EXOSTIV IP?
Can I use optical SFP cables?
How to use the timing constraints generated by Exostiv Dashboard for Intel?
'Failed to assign pinout' error
Using 'Design Checkpoint' (DCP) flow type
How do I update the MICA board configuration?
Can I share transceiver resources between EXOSTIV IP and the design?
How many nodes can I sample continuously without creating overflows?
How do I remove EXOSTIV IP from my netlist to restart insertion?
How can I easily wire my IP throughout hierarchy in RTL flow?
EXOSTIV Probe cannot connect to the target design. What now?
What is 'Storage Qualification'?
Can the EXOSTIV Probe provide the transceiver clock?
Why do I get an 'overflow'?
Can I probe multiple clock domains?
Can I use Synplify instead of the FPGA vendor synthesis tool?
How many FPGA nodes can I connect to EXOSTIV IP?
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Troubleshooting
Can I use transceivers located in separate quads for the same IP instance?
EXOSTIV Dashboard-M – Release Notes
How do I know if my capture unit is able to stream data?
Microchip FPGA: which files are produced in RTL flow and how do I use them?
I have a permanent / perpetual license, but I see it has expired. What happened?
My license is not activated anymore!
How to check the expiration date of my node-locked license?
How do I set up the Exostiv Dashboard client to lease floating licenses from the server?
Core inserter error - ERROR: [Common 17-165] Too many positional options when parsing
Intel FPGA: which files are produced in RTL flow and how do I use them?
Error : 0x80030103
Vivado core generation stops unexpectedly
Segmentation fault (core dumped) QT_QPA_PLATFORM_PLUGIN_PATH - crash
Known issue: GTH bug can result in CPLL in failure state
I have connected the probe to my PC or Mac. The Exostiv Probe connect status is still not on. What's wrong?
The application crashes when connecting to the probe or updating the firmware
Project file name, directory name and directory permissions
Exostiv Dashboard cannot link to Vivado. What happens?
Core insertion is cancelled at 'Starting Vivado Shell' step
Core insertion gets cancelled immediately. What happens?
Should I use Linux or Windows for best software performance?
How to use libusb without administrator privileges?
I cannot lease a floating license in Debian 9 / Debian Stretch
Can I activate the license through a proxy?
Vivado DRC error - PLDS-1 rule violation encountered. What does this mean?
Can I use optical SFP cables?
Can I run Vivado and Exostiv Dashboard on separate machines for netlist core insertion?
How do I match transceivers on my board with these on the probe?
The front panel LED is blinking on EXOSTIV Probe. What does it mean?
How to use the timing constraints generated by Exostiv Dashboard for Intel?
Windows cannot install the driver automatically. What now?
'Failed to assign pinout' error
I cannot connect to the probe over USB
EXOSTIV Dashboard-I – Release Notes
EXOSTIV Dashboard-A – Release Notes
I received an unexpected overflow error with a burst size smaller than 256 or 512 samples. What happens?
Once in a while, the Probe disconnects from the PC. What happened?
I cannot activate my license online. What now?
How do I update the MICA board configuration?
What is the 'Vivado link timeout' setting?
I cannot see the EXOSTIV button in Vivado
Which frequencies are supported for the transceivers reference clock?
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