Visibility into the FPGA.

How is EXOSTIV IP set up and generated?

How is EXOSTIV IP set up and generated?

EXOSTIV Dashboard calls the FPGA vendor tool (Vivado for Xilinx and Quartus for Intel/Altera) to run a synthesis of the EXOSTIV IP and generate the output files.
If the netlist flow is used, EXOSTIV Dashboard interacts with the vendor tool to insert the synthesize EXOSTIV IP into the target design and run the ‘instrumented design’ implementation.
Hence, the ‘quality’ of synthesis and implementation is the quality provided by the FPGA vendor tools.

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