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How to prevent Synplify from changing the net names?

How to prevent Synplify from changing the net names?

Currently applies to EXOSTIV for Xilinx, netlist insertion mode.

When inserting EXOSTIV IP in netlist / automated mode, it is desirable that net names are not changed during synthesis.
Vivado provides the ‘MARK_DEBUG’ attribute to select the nets that will be debugged. This attributes directs Vivado Synthesis to keep them in a special list and preserve their names.

The following discussion from Xilinx’ forum provides guidelines about how to do this with Synplify:
https://forums.xilinx.com/t5/Synthesis/How-to-prevent-Synplify-Pro-changing-the-net-name/td-p/126426.

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