Visibility into the FPGA.

RTL IP core insertion limitations

RTL IP core insertion limitations

– When sharing the transceivers clock signals between EXOSTIV IP and another functionality, this clock signal name must be this of the EXOSTIV IP provided pinout. If this rule is not followed,
the constraints provided with EXOSTIV IP won’t be properly applied.
– the IP signal names must remain unchanged across the design hierarchy: please keep the signal names as provided in the example instantiation file (*.vo for Verilog and *.vho for VHDL).

Failing to follow the above rules results in timing constraints not being properly applied. As a result, the EXOSTIV IP won’t be properly implemented and will not connect to the probe.

Up to EXOSTIV Dashboard software version 1.6.0, the following limitations apply when inserting the EXOSTIV IP with the RTL flow:
– the IP should be inserted at the design top-level. From software version 1.6.1, this constraint does not apply anymore.