Visibility into the FPGA.

Using ‘Design Checkpoint’ (DCP) flow type

Using ‘Design Checkpoint’ (DCP) flow type

Applies to EXOSTIV for Xilinx.
Using Vivado with and without project file (.xpr)
Xilinx Vivado uses project files (.xpr) by default.
In some cases, however, project files are not used – especially when the target FPGA design is not synthesized with Vivado, but with a third-party EDA sythesis tool (such as Synplify).
In this case, ‘Design Checkpoints’ can be used (.dcp). The description that follows shows how to use the EXOSTIV netlist flow with a design checkpoint.

Flow

1) No Vivado project file is used or defined.
2) Synthesize your design with the synthesis tool of your choice.
3) The synthesized design has to be loaded into Vivado. Please check Vivado documentation to know how to use a synthesized design (netlist) as a start point and load it into Vivado.
–> Once loaded, a ‘design checkpoint’ can be saved > this is the start point for using EXOSTIV netlist flow, as EXOSTIV requires a synthesized design to be loaded into Vivado.
4) Once the synthesized design is loaded into Vivado (or the corresponding pre-saved design checkpoint (DCP)), use the ‘Vivado button’ to establish a link between Vivado and EXOSTIV Dashboard.
5) Define EXOSTIV IP structure and nets with EXOSTIV Dashboard (Link Configuration + Capture Configuration).
6) Proceed with EXOSTIV IP insertion, with the following options selected:

– Do no select ‘Implement Design’ nor ‘Generate Bitstream’ in the EXOSTIV Core Insertion flow: Vivado provides 2 sets of commands for running implementation. The command set using project (.xpr) is different from the ‘non-project mode’. EXOSTIV Dashboard currently includes the ‘project mode’ set of commands, that cannot be used automatically in non-project mode’ (DCP).

7) Run the flow by pressing the ‘Insert EXOSTIV IP’ button.
8) After the end of the process, save your EXOSTIV Dashboard project file.
9) From there, the implementation of the instrumented design must be started from the Vivado interface: switch to Vivado. The EXOSTIV IP (default name ‘exi_top’) should be inserted in the design.

10) Use the following sequence of commands from the Vivado command line interface:
– Opt_desing
– (optionally: power_opt_design)
– Place_design
– (optionally: phys_opt_design)
– Route_design
– Write_bitstream

Please refer to the Vivado command line / btach mode user’s guide for additional details and options.

At the end of this process, you obtain a bitstream file ready to be loaded into your target FPGA. You can then use EXOSTIV Analyzer.

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