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Which files are produced in RTL flow and how do I use them?

Which files are produced in RTL flow and how do I use them?

Exostiv Dashboard for Intel

From Exostiv Dashboard version 1.8.4

  • <instance name>_pinout.tcl. Assigns the additional pins required with EXOSTIV IP.
  • <instance name>_sources.tcl. Adds the required source files to the Quartus project for use with EXOSTIV IP

1) Please open the file <instance name>_sources.tcl with a text editor and follow the instructions about ‘relative paths’ and .qdb partitioning (qdb partitioning only applies when Quartus Prime PRO is used). The instructions are enclosed in the comments in these files.
2) Please source the 2 above tcl scripts in your .qsf project file. Please make sure to use relative path when referencing the scripts:
Add the following lines to the project .qsf file:
>> source <relative_path>/exi_top_pinout.tcl
>> source <relative_path>/exi_top_sources.tcl
– Example: (click here to download a full .qsf file example – check lines 125 and 126)
source “../../test/IP184-4ch/exi_top_pinout.tcl”
source “../../test/IP184-4ch/exi_top_sources.tcl”
An example of .qsf file is also provided (Sample.qsf).

Please find the list of generated files with their description below:

  • <instance name>.qxp : EXOSTIV IP synthesized netlist.
  • <instance name>_wrapper.vhd : EXOSTIV IP top level wrapper. This module must be instantiated in the target design.
  • <instance name>_wrapper.vho : Example template on how to create a VHDL instance of EXOSTIV IP in the target design.
  • <instance name>_wrapper.vo : Example template on how to create a Verilog instance of EXOSTIV IP in the target design.
  • <instance name>_pinout.tcl : Script containing the pinout constraints required by the EXOSTIV IP
  • <instance name>_timing.sdc : Constraint file with the timing constraints of EXOSTIV IP.
  • <instance name>_wrapper_pkg.vhd : VHDL package containing the types used for the EXOSTIV IP instantiation.
  • exi_sync_reset.vhd : Internal source file for EXOSTIV IP.
  • exi_xcvr_startup_clock.vhd : Internal source file for EXOSTIV IP.
  • exi_xcvr_top.vhd : Internal source file for EXOSTIV IP.
  • exi_refclk_div.qsys : Internal file for EXOSTIV IP.
  • exi_xcvr_fpll.qsys : Internal file for EXOSTIV IP.
  • exi_xcvr_rst.qsys : Internal file for EXOSTIV IP.
  • exi_xcvr_rx.qsys : Internal file for EXOSTIV IP.
  • exi_xcvr_tx.qsys : Internal file for EXOSTIV IP.

For Exostiv Dashboard version 1.8.3 and older

  • <instance name>.qxp* : EXOSTIV IP synthesized netlist.
  • <instance name>_wrapper.vhd* : EXOSTIV IP top level wrapper. This module must be instantiated in the target design.
  • <instance name>_wrapper.vho : Example template on how to create a VHDL instance of EXOSTIV IP in the target design.
  • <instance name>_wrapper.vo : Example template on how to create a Verilog instance of EXOSTIV IP in the target design.
  • <instance name>_pinout.tcl** : Script containing the pinout constraints required by the EXOSTIV IP (like transceivers location).
  • <instance name>_timing.sdc* : Constraint file with the timing constraints of EXOSTIV IP.
  • <instance name>_wrapper_pkg.vhd* : VHDL package containing the types used for the EXOSTIV IP instantiation.
  • xcvr_rx.qsys* : RX transceivers synthesized IP.
  • xcvr_tx.qsys* : TX transceivers synthesized IP.

* Add to Quartus project for synthesis / P&R – Please check this article
** This file must be sourced in the project QSF file: “source <file path>/<instance name>_pinout.tcl”

Exostiv Dashboard for Xilinx

  • <instance name>.edf* : EXOSTIV IP synthesized netlist.
  • <instance name>.vho : Example template on how to create a VHDL instance of EXOSTIV IP in the target design.(file is called <instance name>.vhd before version 1.7.x)
  • <instance name>.vo : Example template on how to create a Verilog instance of EXOSTIV IP in the target design.(from version 1.7.x)
  • <instance name>_pinout.xdc* : Constraint file for EXOSTIV IP pinout. (like transceivers location).
  • <instance name>_timing.tcl** : Constraint file with the timing constraints of EXOSTIV IP.
  • <instance name>_pkg.vhd* : VHDL package containing the types used for the EXOSTIV IP instantiation.

* Add to Vivado project for synthesis / P&R
** This file must be sourced in the project between synthesis and implementation: “source -notrace <instance name>_timing.xdc”

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