10 things you should know before SoC Validation 1. Validation and verification are different things 2. Emulators do not replace prototypes (and the other way round) 3. There are silicon bugs left to be found during validation 4. Design size matters 5. Each FPGA size matters 6.Read more →
FPGA prototyping with massive visibility is the key to successful validation FPGA prototyping - an essential step of ASIC validation FPGA (Field-Programmable Gate Array) is a key technology for the prototyping of silicon chips and IPs. FPGA use similar silicon processes and is configured on basis ofRead more →
Delivering High Quality Semiconductor IP with confidence Because they are the essential building blocks of modern ASIC and SoC chips, semiconductor IPs are used in a wide variety of environments, in which they are in service during extended times. Verifying that they run flawlessly in all theseRead more →
Is FPGA Prototyping really optional? We conducted a survey on LinkedIn 2 weeks ago about the usage of FPGA prototyping vs. Emulation vs. Simulation. By no means this survey is representative of the whole industry - the sample is simply too small and probably biaised, as theRead more →
Upgrading FPGA Prototyping for High RTL Debug Productivity The importance of FPGA prototyping Despite important advances in simulation-based validation and emulation, ASIC engineers worldwide keep on using FPGA prototyping systems. Earlier this year, we have seen the launch of a new generation of such systems from multipleRead more →
Exostiv Blade is a Game Changer How it started Exostiv Blade all started from client requests in 2018-2019, especially from ASIC & SoC companies. They were seduced by the capture capabilities of Exostiv from FPGA running at speed - in some cases more powerful than the visibilityRead more →
Exostiv Blade - Scalable visibility from anywhere You might have heard about Exostiv Blade already. From the outside, a lot in this product appears to be a massive scale up of EXOSTIV. I thas got: more ports, more bandwidth, more memory, multi-FPGA, multi-clock domain. In other words:Read more →
Exostiv boosts RTL simulation It is essential to reduce the wasted machine cycles used for simulation workloads. Simulation dominates ASIC/SoC/FPGA verification process 'The 2020 Wilson Research Group ASIC and FPGA Functional Verification Study' reports that an ASIC, SoC or FPGA designer can spend up to 40% ofRead more →
Choosing the ideal FPGA prototype for ASIC and SoC design - White Paper. In the 2020 edition of the Wilson Research Group Verification Survey, Mentor Graphics, a Siemens Business, shows that at least 30% of all respondents designing ASIC or SoC declare using FPGA prototyping, no matterRead more →
EXOSTIV is there – and it is not a monster As you might have noticed, EXOSTIV for Xilinx is now released. With the launch, I have been on the roads to demonstrate the product. The good thing about meeting FPGA engineers is the flurry of questions, ideas
Read more →Does FPGA use define verification and debug? You may be aware that we have run a first survey on FPGA design, debug and verification during the last month. (By the way, many thanks to our respondents – we’ll announce the Amazon Gift Card winner in September). In
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