Record FPGA data during 1 hour – really

Record FPGA data during 1 hour - really
Record FPGA data during 1 hour - really. As ASIC, SoC and FPGA engineers, we are used to watching the operation of our designs based on single limited snapshots. RTL simulations, for instance, provide bit-level details during execution times that span over a few (milli)seconds at best.Read more

Defining targets (for FPGA debug)

Defining targets (for FPGA debug) I recently attended a technical seminar organized in The Netherlands by one of the major FPGA vendors (hint: it is one of the 2 top vendors among the '4 + now single outsider' players in the very stable FPGA market). During theRead more