Visibility into the FPGA.

Posts Tagged Ultrascale

Record 8GB from a running FPGA – really

Record 8GB from a running FPGA – really.

In this blog post, I demonstrate 2 different – and extreme? – capture scenarios made possible with EXOSTIV.

In the 2 cases, I have used a VCU108 Virtex Ultrascale development kit from Xilinx.
(see Xilinx’coverage of EXOSTIV in the XCell daily blog here.).

In this setup, a total of 50 Gbps bandwidth over 4 transceiver channels is available (12.5 Gbps per channel). A 4xSFP+ to QSFP+ cable was used between the probe and the target board.

Example 1: Capturing 8GB data in bursts over more than 1 hour

Example 2: Capturing a long continuous single burst of data

As you can see with the examples above, there can be many capture scenarios and options with EXOSTIV.
It is important to note that using bursts is not a fallback for not being able to stream data continuously.
It is true that the total bandwidth that you can afford on the transceivers will affect your ability to stream data continuously or not. Actually, the average available bandwidth defines the sample width that you can send continuously on your transceiver connection with EXOSTIV Probe (if you’d like to do some math about capture units width, please go to this knowledge base article: ‘How many nodes can I sample continuously without creating overflows?’).

However, you should take the following into account:

EXOSTIV extracts samples from FPGA at speed of operation, using internal clocks. While this means that you really see an FPGA in action from inside – this great feature also means that you’ll use clocks at 80 MHz, 100 MHz or even 400 MHz! The EXOSTIV Probe has a 8 Gigabyte memory and provides up 50 Gbps bandwidth.

At 200 MHz, you’ll be able to capture 50,000 / 200 = 250 bits continuously – that is 31.25 bytes.

8 Gigabytes of memory will be filled in with about 1.31 seconds of capture… Not bad.

If your goal is to observe FPGA over longer times, like during hours, you’ll need to define triggers and data qualification conditions in order to lower the average bandwidth needs.
The advantage? You focus on what’s really important in the data that is captured, you potentially enlarge the vector size and you cover more of the FPGA behaviour…

You can even define a reduced capture unit for continuous captures on a limited number of nodes, and an extended capture unit for some details or for burst captures spanning over longer times. Bottom line: Yes, you can have the best of both worlds with the same EXOSTIV IP.

Thank you for reading.
– Frederic

EXOSTIV is in Xilinx’ XCell daily blog!


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