What do you use FPGA prototyping for? Typical usages of FPGA prototyping FPGA Prototyping is used for various purposes. Here are 2 of its main usages: FPGA Debug: at some point of the FPGA design cycle, tests have to be run with a 'real' FPGA board toRead more →
FPGA prototyping with massive visibility is the key to successful validation FPGA prototyping - an essential step of ASIC validation FPGA (Field-Programmable Gate Array) is a key technology for the prototyping of silicon chips and IPs. FPGA use similar silicon processes and is configured on basis ofRead more →
What are the key features of ideal ASIC prototypes? It seems that there has never been a better time to prototype IP, ASIC or SoC with FPGAs. With 35 to 40 billions transistors, the largest FPGA devices on the market can certainly hold quite some share ofRead more →
What can Exostiv Blade do for FPGA prototyping? Classifying FPGA prototyping debug and analysis methodologies. 'FPGA Prototyping' or 'using FPGA boards to prototype an ASIC or a SoC' can be done with a variety of systems. Using such a system requires additional tools to synthesize and partitionRead more →
Exostiv Blade - Managing multiple sites, targets & users In this video, we demonstrate that Exostiv Blade lets you manage multiple sites, target boards and users to reach your FPGA debug, verification and test goals. In a previous demonstration, we already showed that Exostiv Blade core capabilitiesRead more →
Exostiv boosts RTL simulation It is essential to reduce the wasted machine cycles used for simulation workloads. Simulation dominates ASIC/SoC/FPGA verification process 'The 2020 Wilson Research Group ASIC and FPGA Functional Verification Study' reports that an ASIC, SoC or FPGA designer can spend up to 40% ofRead more →
ASIC designers and FPGA OEMs. Last week, we conducted a quick poll on LinkedIn - about what our followers and readers made of FPGA... See the results below: So, 24 of the respondents use FPGA as a target technology ((46% + 23%) x 35) - and 17Read more →
Why Observability matters. At Exostiv Labs, we think that 'Observability' - or 'Visibility' - that is 'the ability to observe (and understand) a system from its I/Os' - is relevant - and even key to FPGA debug. I'd like to show it with a real example takenRead more →
Record FPGA data during 1 hour - really. As ASIC, SoC and FPGA engineers, we are used to watching the operation of our designs based on single limited snapshots. RTL simulations, for instance, provide bit-level details during execution times that span over a few (milli)seconds at best.Read more →
Exostiv - Part 3 - Analyzer Demonstration This is the third and last part of a series of 3 posts that present our flagship product, Exostiv. This is the material that I use as an introduction to Exostiv; it is composed of 3 parts: - Part 1:Read more →
Massive Real-time FPGA Data Capture A game-changer to prevent bug escapes to production. Welcome to this recorded session - thank you for your interest. If you are using AMD Ultrascale™(+) devices then you will be fully aware of the complexity of the designs these FPGAs can holdRead more →
You can capture tons of data. Now what? Offering huge new capabilities is not always seen positively. Sometimes, engineers come to us and ask: 'Now that I am able to collect Gigabytes of trace data from FPGA running at speed... how do I analyze that much data?'.Read more →
If you are using complex FPGA devices then you will be fully aware of the complexity of the designs these FPGAs can hold and the considerable time and effort required to verify the functionality. Even with all the modern design verification techniques available, and extensive lab testing,Read more →
Did you know that Exostiv can send triggers across clock domains? 'Visibility into the FPGA' is a multi-dimensional notion. Obviously, it means 'being able to watch' the inner workings of the chip - and hence, acquire the broadest (over)view on the FPGA. Today, we'll cover another aspectRead more →
Our new waveform viewer is 10x faster! I am happy to announce that Exostiv Dashboard 1.10.0 has been released this week. In addition to the usual maintenance on supporting new devices, new versions of FPGA tools, and a discreet yet fresh icon set update, this is theRead more →
10 cool things about us... #1 Our waveform viewer commonly processes Gigabytes of waves without lagging That's because we have to display data recorded from #FPGA in operation during seconds, minutes or even hours, not just a window of waves from a simulation. So we needed toRead more →
FPGA prototyping platform gets visibility with EXOSTIV This month, thanks to AVNET Israel, we received the ONIX platform for interoperability tests. The board that we received was the AVT-ONIX-VU440-1, equipped with 1 Xilinx Virtex Ultrascale XCVU440 device. The ONIX board system is designed by DgTronix in IsraelRead more →
The FPGA Prototyping problem we are trying to solve 'A la Carte Menu' or 'Full Course Dinner'? Today, choosing a FPGA-based prototyping platform for ASIC or SoC design reduces to 2 choices: - Either you buy or build a FPGA board and choose EDA tools separately; or:Read more →
On-Demand Webinar: 'How to capture Gigabytes of traces from FPGA. At speed.' In this post, you have the opportunity to catch up with our Webinar that ran live earlier this year. In this -now 'on-demand'- webinar we introduce and demonstrate EXOSTIV and show how it can boostRead more →
EXOSTIV lets you peer deeper into FPGA Watch now... EXOSTIV Introduction EXOSTIV's structure (see below) allows deeper data capture from inside FPGA: unlike JTAG instrumentation, EXOSTIV provides an external storage that extends beyond the memory available in the FPGA. Coupled with the usage of transceivers, it createsRead more →
Exostiv provides Gigabytes of visibility into the FPGA running at speed of operation from virtually any board. In this webinar, we'll introduce and demonstrate Exostiv and show how it can boost productivity when designing, debugging and verifying FPGA - and this, whether you use FPGA for ASICRead more →
Record 8GB from a running FPGA - really. In this blog post, I demonstrate 2 different - and extreme? - capture scenarios made possible with EXOSTIV. In the 2 cases, I have used a VCU108 Virtex Ultrascale development kit from Xilinx. (see Xilinx'coverage of EXOSTIV in theRead more →
Deep Trace & Bandwidth Exostiv provides the following maximum capabilities for capturing data from inside FPGA running at speed: Capabilities. 50 Gigabit per second bandwidth for collecting FPGA traces. 8 Gigabyte of memory for trace storage. 32,768 nodes probing simultaneously. 524,288 nodes reach. Actually, we have builtRead more →
EXOSTIV is there – and it is not a monster As you might have noticed, EXOSTIV for Xilinx is now released. With the launch, I have been on the roads to demonstrate the product. The good thing about meeting FPGA engineers is the flurry of questions, ideas
Read more →‘My FPGA debug and verification flow should be improved…’ In my last post, I revealed some of the results of our recent survey on FPGA. These results depicted a ‘flow-conscious’ FPGA engineer, using a reduced mix of methodologies in the flow and very prone to going to
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