FPGA Debug Reloaded.



EXOSTIV™ IP is an intellectual property block that is inserted into the target FPGA to debug in order to reach internal nodes and capture their evolution over time. EXOSTIV™ IP mobilizes available FPGA resources to route signals to be observed, provide triggering and filtering resources, buffer trace information and send it over gigabit transceivers to EXOSTIV™ Probe.

EXOSTIV™ IP has to be configured, synthesized and inserted with EXOSTIV™ Dashboard Core Inserter and the FPGA vendor tool.

Using EXOSTIV™ IP for extracting trace data from FPGA for debug and validations involves using EXOSTIV™ Dashboard software with EXOSTIV™ Probe.


  • Configurable upstream link, using 1 to 4 FPGA transceivers up to 12.5 Gbps
  • Downstream link to configure IP at run-time, without the need to re-implement instrumented design.
  • From 1 to 16 configurable ‘Capture Units’ (CU) to sample FPGA internal nodes, with trigger and data qualification resources and selectable FIFO size.
  • From 1 to 16 multiplexed Data Groups per CU, selectable at run time through downstream link.
  • From 1 to 2,048 bits per Data Group, connected to the target FPGA internal nodes.
  • Cross-Capture Units trigger lines.

Related documentation

Please fill in the form below to download:
UG401 – EXOSTIV™ IP user guide

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