SoC Validation & Debug
Add massive visibility to all FPGA Prototyping platforms.
Freely choose or make your own prototyping platform for validation & debug.
Extreme visibility at speed into FPGA prototypes.
FPGA Prototyping is a key strategic approach to check ASIC hardware and speed up SoC software development when the silicon is not available yet.
Interconnected FPGAs on a board provide the number of gates required to map a complex ASIC and start develop software with some ability to troubleshoot the hardware – most of the time at the expense of the operating frequency, that is reduced to allow partitioning.
At all stages of this process, deep trace debug captures are necessary to navigate complex silicon and make the most of the ASIC validation time. Unfortunately, generic tools (think JTAG) usually provide poor visibility, whereas prototyping platform vendors’tools only work well with their specific platform and cannot be used in any environment or at speed with any board.
Exostiv Labs’ solutions provide deep *gigabyte-range* capture capability at speed of operation from any FPGA board or FPGA prototyping system, thereby providing extreme visibility into all ASIC and SoC prototyping setups.
Combining large external memories and FPGA high-speed transceivers with a highly configurable IP, our solutions allow streaming massive traces from inside the FPGA prototyping system(s) used throughout the ASIC or SoC validation process.
Validating SoC require the right set of tools
A prototyping approach requires properly selecting FPGA board(s) and tools, with the purpose of analyzing the system, collecting data from failed tests (history, ‘post-mortem’, …) and taking action to fix the system.
Important !
- FPGA prototyping boards should be integrated into the target operating environment.
- Running at the target speed of operation allows realistic stimulus / response.
- Scaling down the frequency can be impossible when validating interoperability with external hardware.
- Multiple levels of observability are required: from SoC bus-level down to IP bit-level.
- When using prototyping systems where debug resources don’t scale (storage, bandwidth, nr of nodes, visualization, nr of users, …), you are risking bug escapes to production and endless ‘bug hunting’ sessions.
Add gigantic visibility to your pre-silicon prototyping using FPGA.
If your goals are focused on validation or software development, prototyping is preferable to emulation or simulation as it allows interactions with real-world type of I/O running at speed of operation. Traditional prototyping platforms and house-made prototyping platforms do not usually provide much built-in visibility. Speeds limited to 20-50 MHz are very common and there is only a very limited ability to observe the system at speed (understand narrow scope and short captures). Since you need to carry on debugging even after verification, such limited visibility serioulsy lowers your productivity.
By using the right resources to provide Gigabyte and even Terabyte-range visibility at speed of operation (up to 800 MHz), Exostiv Blade moves your prototyping system up above in these charts.
Run multiple concurrent FPGA prototypes
Duplicating prototyping setup and running parallel concurrent tests are the key to augmenting the test density and coverage*
With Exostiv Blade series, you are able to set up a central appliance to capture massive traces from multiple FPGA prototypes. Our solutions adapt to any FPGA board and provides advanced Python scripting for automation and usage with your continuous integration (CI) system.
*Read this article and find out why it is important.
Manage your prototyping assets and have massive FPGA visibility enterprise-wide.
