Massive real time data capture is essential to FPGA Debug.
FPGA programmability has traditionally enabled engineers to use board prototypes in the lab for debug and verification. Using a system at speed in its ‘real’ environment is used to overcome modeling errors and excessive simulation times.
However, with the unprecedented complexities reached by FPGAs today, the usual JTAG-based embedded logic analyzers hardly provide sufficient visibility on system-under-test and create tough board implementation constraints.
Scale your tools, not your expectations
Over time, the usual JTAG-based tools and traditional instrumentation have failed to provide the visibility required by increasing FPGA complexities.
Prototyping is a must, though. Using a prototype provides much faster execution than simulation and reveals the imperfections of the models we use in simulation. Even with methodologies that include code coverage, testbench coverage, UVM, assertions or constrained random stimuli, prototyping should be part of any advanced verification flow.
Practically, efficient FPGA debug from a board first means ‘large storage’ and ‘large bandwidth’. Without these resources, you cannot get really useful data to understand and fix FPGA bugs before production (see the table to the right ‘Bandwidth and Storage are essential’).
Our solutions for FPGA Debug
Typical solutions are shown below. Customized solutions also available – contact us.
Although it is our entry-level product, Exostiv already provides 100,000 times more visibility into FPGA than the usual JTAG-based solutions included in FPGA development tool suites.
This configuration originates from customers wanting to have a powerful test and debug appliance that can sit on a bench and be reasonably silent... unlike 2U chassis.