FPGA Debug

Capture Gigabytes. At speed.

Our solutions for FPGA Debug

Massive real time data capture is essential to FPGA Debug.

FPGA programmability has traditionally enabled engineers to use board prototypes in the lab for debug and verification. Using a system at speed in its ‘real’ environment is used to overcome modeling errors and excessive simulation times.

However, with the unprecedented complexities reached by FPGAs today, the usual JTAG-based embedded logic analyzers hardly provide sufficient visibility on system-under-test and create tough board implementation constraints.

Scale your tools, not your expectations

Over time, the usual JTAG-based tools and traditional instrumentation have failed to provide the visibility required by increasing FPGA complexities.

Prototyping is a must, though. Using a prototype provides much faster execution than simulation and reveals the imperfections of the models we use in simulation. Even with methodologies that include code coverage, testbench coverage, UVM, assertions or constrained random stimuli, prototyping should be part of any advanced verification flow.

Practically, efficient FPGA debug from a board first means ‘large storage’ and ‘large bandwidth’. Without these resources, you cannot get really useful data to understand and fix FPGA bugs before production (see the table to the right ‘Bandwidth and Storage are essential’).

A use case from the field

Massive real-time data capture, a game changer to prevent bug escapes to production
Massive real-time data capture from FPGA - webinar replay
Video processing systems often make use of FPGA coupled with DDR memory as a frame buffer and run processing both on the write and read side of the memory. These systems are characterized with massive and high speed data flow and the latency introduced by the write / read operation to the external DDR memory.
In this webinar replay, we demonstrate why massive real time data capture capabilities are necessary to resolve a difficult bug case.

The key dimensions of FPGA Debug

Profile of FPGA Debug on common FPGA setup dimensions

Bandwidth and storage are essential

StorageBandwidthEffect 
SmallSmallNo visibility.
Debug strategy on real hardware is hardly usable with complex FPGA chips.

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LargeSmallThe system has scaled for visibility thanks to the large storage, but the limited bandwidth forces stopping the system to collect data stuck inside the FPGA memory.
The environment must be stopped too.The test scenario is not realistic. Execution time can be excessive.

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LargeLargeProvides huge visibility at speed of operation.
Allows debug and verification scenarios in complex environments running at full speed.

You can make the most of a 'hardware-based' approach and explore the behaviour of FPGA in realistic conditions. FAST!

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Our solutions for FPGA Debug

Typical solutions are shown below. Customized solutions also available – contact us.


Why this one?

Did you know that...

Uncompromised performance in a compact and portable enclosure (50 Gbps / 8GB).


Solid alternative to JTAG logic analyzers providing actionable data quantities.

Although it is our entry-level product, Exostiv already provides 100,000 times more visibility into FPGA than the usual JTAG-based solutions included in FPGA development tool suites.

More bandwidth

(100 Gbps, up to 4x25 Gbps)

Remote-controllable over network

Remote-controllability has been the most requested feature in 2021. Obvious... ?

Multi-user - Ideal for teamwork

Flexible bandwidth supporting multiple target FPGA and single FPGA with port aggregation


Total 400 Gbps bandwidth for more real time capture performance

Remote-controllable over network

This configuration originates from customers wanting to have a powerful test and debug appliance that can sit on a bench and be reasonably silent... unlike 2U chassis.