The FPGA Prototyping problem we are trying to solve

The FPGA Prototyping problem we are trying to solve
The FPGA Prototyping problem we are trying to solve 'A la Carte Menu' or 'Full Course Dinner'? Today, choosing a FPGA-based prototyping platform for ASIC or SoC design reduces to 2 choices: - Either you buy or build a FPGA board and choose EDA tools separately; or:Read more

How to capture gigabytes of traces from FPGA. At speed.

How to capture gigabytes of traces from FPGA. At speed.
On-Demand Webinar: 'How to capture Gigabytes of traces from FPGA. At speed.' In this post, you have the opportunity to catch up with our Webinar that ran live earlier this year. In this -now 'on-demand'- webinar we introduce and demonstrate EXOSTIV and show how it can boostRead more

EXOSTIV lets you peer deeper into FPGA

EXOSTIV lets you peer deeper into FPGA
EXOSTIV lets you peer deeper into FPGA Watch now... EXOSTIV Introduction EXOSTIV's structure (see below) allows deeper data capture from inside FPGA: unlike JTAG instrumentation, EXOSTIV provides an external storage that extends beyond the memory available in the FPGA. Coupled with the usage of transceivers, it createsRead more

What are the key features of ideal ASIC prototypes?

What are the key features of ideal ASIC prototypes?
What are the key features of ideal ASIC prototypes? It seems that there has never been a better time to prototype ASIC or SoC with FPGAs. The recent announcement from leading FPGA vendors (such as this one, from Intel), show that the biggest FPGAs now reach moreRead more

Pick a FPGA board, please

Pick a FPGA board, please
Pick a FPGA board, please. Things to check before you use Exostiv... 'Using Exostiv requires having a board to which the Exostiv probe can be connected.' Of course. If you are considering using Exostiv, that's great, but you first need to check if the right kind ofRead more

Exostiv boosts RTL simulation

Exostiv boosts RTL simulation
Exostiv boosts RTL simulation It is essential to reduce the wasted machine cycles used for simulation workloads. Simulation dominates ASIC/SoC/FPGA verification process 'The 2018 Wilson Research Group ASIC and FPGA Functional Verification Study' (you may have to register for free to watch this) reports that an ASIC,Read more

Exostiv supports Intel Stratix 10 FPGA

Exostiv supports Intel Stratix 10 FPGA
Exostiv supports Intel Stratix 10 FPGA As Intel Stratix 10 FPGA gets deployed for real applications, we are ready too at Exostiv Labs! Stratix 10 devices are supported from Exostiv Dashboard for Intel v. 1.8.4 (and stay tuned, because Cyclone 10 FPGA are around the corner...). WeRead more

Record FPGA data during 1 hour – really

Record FPGA data during 1 hour - really
Record FPGA data during 1 hour - really. As ASIC, SoC and FPGA engineers, we are used to watching the operation of our designs based on single limited snapshots. RTL simulations, for instance, provide bit-level details during execution times that span over a few (milli)seconds at best.Read more

Deep Trace & Bandwidth

Deep Trace & Bandwidth
Deep Trace & Bandwidth Exostiv provides the following maximum capabilities for capturing data from inside FPGA running at speed: Capabilities. 50 Gigabit per second bandwidth for collecting FPGA traces. 8 Gigabyte of memory for trace storage. 32,768 nodes probing simultaneously. 524,288 nodes reach. Actually, we have builtRead more