RTL or Netlist flow?

RTL or Netlist flow?

RTL or Netlist flow? EXOSTIV Dashboard Core Inserter and Exostiv Blade Core Inserter propose 2 alternate flows* for inserting EXOSTIV IP and Exostiv Blade IP into the target design: the ‘RTL flow’ and the ‘Netlist flow’. With the RTL flow, the IP is generated as a RTL

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What can Exostiv Blade do for FPGA prototyping?

What can Exostiv Blade do for FPGA prototyping?
What can Exostiv Blade do for FPGA prototyping? Classifying FPGA prototyping debug and analysis methodologies. 'FPGA Prototyping' or 'using FPGA boards to prototype an ASIC or a SoC' can be done with a variety of systems. Using such a system requires additional tools to synthesize and partitionRead more

What do you use FPGA prototyping for?

What do you use FPGA prototyping for?
What do you use FPGA prototyping for? Typical usages of FPGA prototyping FPGA Prototyping is used for various purposes. Here are 3 of its main usages: FPGA Debug: at some point of the FPGA design cycle, tests have to be run with a 'real' FPGA board toRead more

Is FPGA Prototyping really optional?

Is FPGA Prototyping really optional?
Is FPGA Prototyping really optional? We conducted a survey on LinkedIn 2 weeks ago about the usage of FPGA prototyping vs. Emulation vs. Simulation. By no means this survey is representative of the whole industry - the sample is simply too small and probably biaised, as theRead more

Upgrading FPGA Prototyping for High RTL Debug Productivity

Upgrading FPGA Prototyping for High RTL Debug Productivity
Upgrading FPGA Prototyping for High RTL Debug Productivity The importance of FPGA prototyping Despite important advances in simulation-based validation and emulation, ASIC engineers worldwide keep on using FPGA prototyping systems. Earlier this year, we have seen the launch of a new generation of such systems from multipleRead more

Exostiv Blade is a Game Changer

Exostiv Blade is a Game Changer
Exostiv Blade is a Game Changer How it started Exostiv Blade all started from client requests in 2018-2019, especially from ASIC & SoC companies. They were seduced by the capture capabilities of Exostiv from FPGA running at speed - in some cases more powerful than the visibilityRead more

Exostiv boosts RTL simulation

Exostiv boosts RTL simulation
Exostiv boosts RTL simulation It is essential to reduce the wasted machine cycles used for simulation workloads. Simulation dominates ASIC/SoC/FPGA verification process 'The 2020 Wilson Research Group ASIC and FPGA Functional Verification Study' reports that an ASIC, SoC or FPGA designer can spend up to 40% ofRead more

ASIC designers and FPGA OEMs

ASIC designers and FPGA OEMs
ASIC designers and FPGA OEMs. Last week, we conducted a quick poll on LinkedIn - about what our followers and readers made of FPGA... See the results below: So, 24 of the respondents use FPGA as a target technology ((46% + 23%) x 35) - and 17Read more

Why observability matters

Why observability matters
Why Observability matters. At Exostiv Labs, we think that 'Observability' - or 'Visibility' - that is 'the ability to observe (and understand) a system from its I/Os' - is relevant - and even key to FPGA debug. I'd like to show it with a real example takenRead more

The future of FPGA

The future of FPGA
The future of FPGA Quite unusually, I'd like to share some random thoughts about the evolution of our industry. It has escaped to no one, these are exciting times, with tech giants scrambling to build the most successful company in computing. As you see with the pictureRead more

Record FPGA data during 1 hour – really

Record FPGA data during 1 hour - really
Record FPGA data during 1 hour - really. As ASIC, SoC and FPGA engineers, we are used to watching the operation of our designs based on single limited snapshots. RTL simulations, for instance, provide bit-level details during execution times that span over a few (milli)seconds at best.Read more

Exostiv – Part 1 – Presentation

Exostiv - Part 1 - Presentation
Exostiv - Part 1 - Presentation This is the first part of a series of 3 posts that present our flagship product, Exostiv. This is the material that I use as an introduction to Exostiv; it is composed of 3 parts: - Part 1: Presentation, based onRead more

You can capture tons of data. Now what?

You can capture tons of data. Now what?
You can capture tons of data. Now what? Offering huge new capabilities is not always seen positively. Sometimes, engineers come to us and ask: 'Now that I am able to collect Gigabytes of trace data from FPGA running at speed... how do I analyze that much data?'.Read more

What are your ready to mobilize for FPGA debug?

What are your ready to mobilize for FPGA debug?

What are you ready to waste mobilize? I believe that there are 3 common misconceptions about debugging FPGA with the real hardware: Misconception #1: Debugging happens because the engineers are incompetent. Misconception #2: FPGA debugging on hardware ‘wastes’ resources. Misconception #3: A single methodology should solve ALL

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Deep Trace & Bandwidth – an update

Deep Trace & Bandwidth - an update
Deep Trace & Bandwidth - an update Exostiv has been around since 2015 and hundreds of engineers have adopted it since then. They design FPGA-based equipment or use FPGA to prototype ASIC. They work in very different industries - Defense & Aerospace, Semiconductors, Broadcast, Media, Medical, Telecommunications,Read more

Get your money back in 4 weeks

Get your money back in 4 weeks
Get your money back in 4 weeks Debug productivity is notoriously hard to sell. Engineers who ask budgets for debugging tools are still too often blamed by the Management for creating the bugs in first instance. ('Why would I pay more for correcting the bugs that YOURead more

Our waveform viewer is 10x faster

Our waveform viewer is 10x faster
Our new waveform viewer is 10x faster! I am happy to announce that Exostiv Dashboard 1.10.0 has been released this week. In addition to the usual maintenance on supporting new devices, new versions of FPGA tools, and a discreet yet fresh icon set update, this is theRead more

10 cool things about us…

10 cool things about us...
10 cool things about us... #1 Our waveform viewer commonly processes Gigabytes of waves without lagging That's because we have to display data recorded from #FPGA in operation during seconds, minutes or even hours, not just a window of waves from a simulation. So we needed toRead more

EXOSTIV lets you peer deeper into FPGA

EXOSTIV lets you peer deeper into FPGA
EXOSTIV lets you peer deeper into FPGA Watch now... EXOSTIV Introduction EXOSTIV's structure (see below) allows deeper data capture from inside FPGA: unlike JTAG instrumentation, EXOSTIV provides an external storage that extends beyond the memory available in the FPGA. Coupled with the usage of transceivers, it createsRead more

Record 8GB from a running FPGA – really

Record 8GB from a running FPGA - really
Record 8GB from a running FPGA - really. In this blog post, I demonstrate 2 different - and extreme? - capture scenarios made possible with EXOSTIV. In the 2 cases, I have used a VCU108 Virtex Ultrascale development kit from Xilinx. (see Xilinx'coverage of EXOSTIV in theRead more

Pick a FPGA board, please

Pick a FPGA board, please
Pick a FPGA board, please. Things to check before you use Exostiv... 'Using Exostiv requires having a board to which the Exostiv probe can be connected.' Of course. If you are considering using Exostiv, that's great, but you first need to check if the right kind ofRead more

Exostiv supports Intel Stratix 10 FPGA

Exostiv supports Intel Stratix 10 FPGA
Exostiv supports Intel Stratix 10 FPGA As Intel Stratix 10 FPGA gets deployed for real applications, we are ready too at Exostiv Labs! Stratix 10 devices are supported from Exostiv Dashboard for Intel v. 1.8.4 (and stay tuned, because Cyclone 10 FPGA are around the corner...). WeRead more

Deep Trace & Bandwidth

Deep Trace & Bandwidth
Deep Trace & Bandwidth Exostiv provides the following maximum capabilities for capturing data from inside FPGA running at speed: Capabilities. 50 Gigabit per second bandwidth for collecting FPGA traces. 8 Gigabyte of memory for trace storage. 32,768 nodes probing simultaneously. 524,288 nodes reach. Actually, we have builtRead more

Debug with reduced footprint

Debug with reduced footprint
Debug with reduced footprint Footprint, 'real estate', resources, ... No matter the design complexity, allocating resources to debugging is something you'll worry about. If you are reading these lines, it is likely that you have some interest in running some of your system debugging from a realRead more

Debugging FPGAs at full speed

Debugging FPGAs at full speed
Debugging FPGAs at full speed In my previous post, I explained why increasing the available 'window of visibility' is a gigantic advantage when tracking system-level issues on modern complex FPGAs. EXOSTIV's structure does not require the FPGA internal memory to grow with the depth of the capture.Read more

Does FPGA use define verification and debug?

Does FPGA use define verification and debug? You may be aware that we have run a first survey on FPGA design, debug and verification during the last month. (By the way, many thanks to our respondents – we’ll announce the Amazon Gift Card winner in September). In

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Defining targets (for FPGA debug)

Defining targets (for FPGA debug) I recently attended a technical seminar organized in The Netherlands by one of the major FPGA vendors (hint: it is one of the 2 top vendors among the '4 + now single outsider' players in the very stable FPGA market). During theRead more