FPGA Debug Reloaded.

Getting Started

Getting Started with EXOSTIV

EXOSTIV, Netlist flow

(Applies to EXOSTIV for Xilinx)

EXOSTIV,RTL Flow

(Applies to EXOSTIV for Xilinx and EXOSTIV for Intel)

– Load target FPGA with the generated bitstream…
– Once the EXOSTIV Probe is connected to your PC with the USB cable, and powered-on, click on the ‘Connect’ icon on the EXOSTIV Dashboard toolbar:

… and there you go for analyzing and debugging your target design.

EXOSTIV Analyzer


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