Extreme visibility at speed into FPGA prototype.
FPGA Prototyping is a key strategic approach to check ASIC hardware and speed up SoC software development when the silicon is not available yet.
Interconnected FPGAs on a board provide the number of gates required to map a complex ASIC and start develop software with some ability to troubleshoot the hardware – most of the time at the expense of the operating frequency, that is reduced to allow partitioning.
At all stages of this process, deep trace debug captures are necessary to navigate complex silicon and make the most of the ASIC validation time. Unfortunately, generic tools (think JTAG) usually provide poor visibility, whereas prototyping platform vendors’tools only work well with their specific platform and cannot be used in any environment or at speed with any board.
Exostiv Labs’ solutions provide deep *gigabyte-range* capture capability at speed of operation from any FPGA board or FPGA prototyping system, thereby providing extreme visibility into all ASIC and SoC prototyping setups.
Combining large external memories and FPGA high-speed transceivers with a highly configurable IP, our solutions allow streaming massive traces from inside the FPGA prototyping system(s) used throughout the ASIC or SoC validation process.
Choose your ASIC prototyping system. Again.
Choosing and setting up an ASIC prototype with FPGAs can be complex. It supposes finding an answer to many questions:
– Will you buy it or make it?
– Do you need a single prototyping platform or does it have to evolve during the validation process?
– How will the prototype be interfaced with its target environment?
No matter if you use a commercial system* or your own platform designed in-house, our solutions adapt to all of them:
- Xilinx FPGA support: Series 7, Ultrascale and Ultrascale+.
- Standard connectivity with FPGA boards: FMC, SFP+, QSFP+, QSFP28, Samtec ERF6/ERM6, SATA – and more.
- Use any tool for FPGA synthesis
Our solutions for FPGA Prototyping
Typical solutions are shown below. Customized solutions also available – contact us.
FPGA prototyping frequently involves partitioning the future ASIC or SoC onto multiple FPGAs. Because of bottlenecks at the interfaces between FPGAs, speed is reduced.