FPGA Prototyping

Add massive visibility to all platforms.

Freely choose or make your own prototyping platform.

Our solutions for FPGA Prototyping

Extreme visibility at speed into FPGA prototype.

FPGA Prototyping is a key strategic approach to check ASIC hardware and speed up SoC software development when the silicon is not available yet.
Interconnected FPGAs on a board provide the number of gates required to map a complex ASIC and start develop software with some ability to troubleshoot the hardware – most of the time at the expense of the operating frequency, that is reduced to allow partitioning.

At all stages of this process, deep trace debug captures are necessary to navigate complex silicon and make the most of the ASIC validation time. Unfortunately, generic tools (think JTAG) usually provide poor visibility, whereas prototyping platform vendors’tools only work well with their specific platform and cannot be used in any environment or at speed with any board.

Exostiv Labs’ solutions provide deep *gigabyte-range* capture capability at speed of operation from any FPGA board or FPGA prototyping system, thereby providing extreme visibility into all ASIC and SoC prototyping setups.

Combining large external memories and FPGA high-speed transceivers with a highly configurable IP, our solutions allow streaming massive traces from inside the FPGA prototyping system(s) used throughout the ASIC or SoC validation process.

Choose your ASIC prototyping system. Again.

Choosing and setting up an ASIC prototype with FPGAs can be complex. It supposes finding an answer to many questions:
– Will you buy it or make it?
– Do you need a single prototyping platform or does it have to evolve during the validation process?
– How will the prototype be interfaced with its target environment?

No matter if you use a commercial system* or your own platform designed in-house, our solutions adapt to all of them:

  • Xilinx FPGA support: Series 7, Ultrascale and Ultrascale+.
  • Standard connectivity with FPGA boards: FMC, SFP+, QSFP+, QSFP28, Samtec ERF6/ERM6, SATA – and more.
  • Use any tool for FPGA synthesis
* AMD-Xilinx maintains a list of references on this page.

The key dimensions of FPGA Prototyping

Profile of FPGA prototyping on common FPGA prototypes dimensions

FPGA Prototyping is characterized by:

  • A ‘large’ number of gates.
  • Except for small ASICs, the prototype is composed of multiple FPGA chips.
  • The need to look everywhere in the design, essentially at internal bus levels. IPs are supposedly already validated, so, the overal ASIC or SoC ‘skeleton’ is where you’ll want to look at. This applies to when hardware is used to check software behaviour.
  • At speed operation is rare because the ASIC or the SoC is partitioned onto multiple FPGA devices. Most of the time, time division multiplexing is necessary at the interface between the FPGAs, forcing to reduce the overall frequency.

Our solutions improve FPGA Prototyping

Exostiv Blade boosts FPGA prototypes' visibility expressed as number of nodes
Exostiv Blade boosts FPGA prototypes' visibility expressed as number of cycles

Our solutions for FPGA Prototyping

Typical solutions are shown below. Customized solutions also available – contact us.

Key features


Total 450 Gbps to 1.350 Tbps bandwidth real time capture performance from FPGA, enabling extended view on system busses and correlation with software trace.

4 to 12 connection ports to connect multiple FPGA

Compatible with major commercial FPGA prototyping systems and BYO boards.

Multi-user & remote-controllable, allowing 24/7 operation for prototyping systems shared by a global team.

FPGA prototyping frequently involves partitioning the future ASIC or SoC onto multiple FPGAs. Because of bottlenecks at the interfaces between FPGAs, speed is reduced.

Using a slowed down platform for hardware debug and software development can be ok but the required bandwidth needs for extracting data will still be high, the number of nodes to be observed compensating the frequency reduction.

Consequently, the mix of using multiple FPGA chips, having to look at a lot of nodes and the nature of software debug requires from a visibility platform to provide: large bandwidth, a large number of ports to access multiple chips and very deep memory to store the traces.