IP Verification

Test IP at speed in target environment

Our solutions for IP Verification

Run tests with actionable visibility.

Quality IPs require running large number of cycles in target conditions

Releasing an IP for integration in other designs requires going through extensive testing in realistic conditions to cover the largest number of usage scenarios. IP Verification run with FPGA prototypes is extremely cost-effective:


  • FPGA prototyping boards can reproduce the target operating environment.
  • Running at the target speed of operation allows realistic external world stimulus / response.
  • IP can fit into a single or small number of FPGAs with no need for complex partitioning.

As shown in the figure on the right, IP Verification has got a specific ‘profile’.

Running at speed of operation requires fitting the IP in the smallest number of FPGA chips to avoid partitioning when possible. IP having to interact with real world peripherals – such as interface IPs – often have to run at high frequency (multiples of 100 MHz). Also, the number of gates required to map a single IP can be kept low compared to complete ASIC verification. Finally, IP Verification requires observing down to the bit level – and not just at the IP external interfaces.

Master IP complexity with proper observation resources

At the very least, FPGA prototypes used to verify IP should include the software controls to sequence and run the desired test scenarios. This includes the ability to ‘inject’ the right test vectors into the IP under test, preferably generated from a faithful model of the environment, if not from the target environment itself. With the IP running at speed, productivity can be very high.

The test environment should have the facilities to extract test pass / fail test results. Depending on the IP, the results can be limited to software and other test IP log messages.

While this method is fine as long as the tests pass, it particularly lacks details in case a test fails. In this case, massive and cycle-accurate captures and the ability to roll back into history prove extremely useful, as the engineer is able to look into simulation-like waveform to troubleshoot the design. Adding the ability to watch the IP ‘from inside’ at speed of operation during a long number of cycles is of tremendous value. Reproducing a failure – even when it is random – is extremely fast and the ability to explore the IP at bit level provides the right resolution level. (add something about the freedom to choose the board because we are compatible)

Run multiple concurrent FPGA prototypes

Duplicating prototyping setup and running parallel concurrent tests are the key to augmenting the test density and coverage*

With Exostiv Blade series, you are able to set up a central appliance to capture massive traces from multiple FPGA prototypes. Our solutions adapt to any FPGA board and provides advanced Python scripting for automation and usage with your continuous integration (CI) system.

Manage your prototyping assets and have massive FPGA visibility enterprise-wide.


*Read this article and find out why it is important.

Deliver IP to production with massive confidence. Now.

The key dimensions of IP Verification

Profile of IP verification on common FPGA prototypes dimensions

IP Verification is characterized by:

  • A ‘low’ number of gates: a single IP is intrisically smaller than a full SoC.
  • The prototype is composed of a single large FPGA or a small number of FPGAs.
  • The need to look deep into the IP. You’ll want your IP to have been touroughly examined.
  • The need to extensively test the IP in a complete set of realistic conditions. IPs make sense if they can be reused in a wide variety of scenarios. The execution speed of a prototype is instrumental to this end.
  • The need to operate at target speed, especially for interface IPs and IPs operating with existing peripherals.

What you need is bit-level massive capture at speed.

IP Verification setup

Our solutions for IP Verification

Typical solutions are shown below. Customized solutions also available – contact us.


Key features

Rationales

Total 400 Gbps to 1.2 Tbps bandwidth real time capture performance from FPGA

4 to 12 connection ports to run test scenarios in parallel from duplicate target IPs and increase coverage.

Remote-controllable over network

Multi-user

Advanced Python interface for session automation


Easily usable within CI environments

IP Verification requires running extended cycles to verify the functionalities in a collection of scenarios that guarantee the best coverage. Running parallel tests from duplicate FPGA targets lets you augment coverage faster.


At speed execution is needed to verify IP interoperability - especially for interface IPs.

For this reason, the total available bandwidth and a large number of ports help tackling complex IP verification cases.

Finally, Exostiv Blade's Python interface enable job automation and allows including Exostiv Blade in CI environment.