Run tests with actionable visibility.
Quality IPs require running large number of cycles in target conditions
Releasing an IP for integration in other designs requires going through extensive testing in realistic conditions to cover the largest number of usage scenarios. IP Verification run with FPGA prototypes is extremely cost-effective:
As shown in the figure on the right, IP Verification has got a specific ‘profile’.
Running at speed of operation requires fitting the IP in the smallest number of FPGA chips to avoid partitioning when possible. IP having to interact with real world peripherals – such as interface IPs – often have to run at high frequency (multiples of 100 MHz). Also, the number of gates required to map a single IP can be kept low compared to complete ASIC verification. Finally, IP Verification requires observing down to the bit level – and not just at the IP external interfaces.
Master IP complexity with proper observation resources
At the very least, FPGA prototypes used to verify IP should include the software controls to sequence and run the desired test scenarios. This includes the ability to ‘inject’ the right test vectors into the IP under test, preferably generated from a faithful model of the environment, if not from the target environment itself. With the IP running at speed, productivity can be very high.
The test environment should have the facilities to extract test pass / fail test results. Depending on the IP, the results can be limited to software and other test IP log messages.
While this method is fine as long as the tests pass, it particularly lacks details in case a test fails. In this case, massive and cycle-accurate captures and the ability to roll back into history prove extremely useful, as the engineer is able to look into simulation-like waveform to troubleshoot the design. Adding the ability to watch the IP ‘from inside’ at speed of operation during a long number of cycles is of tremendous value. Reproducing a failure – even when it is random – is extremely fast and the ability to explore the IP at bit level provides the right resolution level. (add something about the freedom to choose the board because we are compatible)
Run multiple concurrent FPGA prototypes
Duplicating prototyping setup and running parallel concurrent tests are the key to augmenting the test density and coverage*
With Exostiv Blade series, you are able to set up a central appliance to capture massive traces from multiple FPGA prototypes. Our solutions adapt to any FPGA board and provides advanced Python scripting for automation and usage with your continuous integration (CI) system.
Manage your prototyping assets and have massive FPGA visibility enterprise-wide.
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Our solutions for IP Verification
Typical solutions are shown below. Customized solutions also available – contact us.
IP Verification requires running extended cycles to verify the functionalities in a collection of scenarios that guarantee the best coverage. Running parallel tests from duplicate FPGA targets lets you augment coverage faster.
For this reason, the total available bandwidth and a large number of ports help tackling complex IP verification cases.
Finally, Exostiv Blade's Python interface enable job automation and allows including Exostiv Blade in CI environment.