EXOSTIV IP
- Microchip FPGA: which files are produced in RTL flow and how do I use them?
- In netlist insertion mode, how are nets preserved so they can be probed and not removed during logic optimization?
- Issue when using Vivado 2020.2
- AMD FPGA: which files are produced in RTL flow and how do I use them?
- Intel FPGA: which files are produced in RTL flow and how do I use them?
- How do Exostiv Blade IP and Exostiv IP compare?
- Can I use transceivers located in separate quads with the same Exostiv probe?
- What is the ‘User Register’ and how do I use it?
- Which files are produced in RTL flow and how do I use them?
- ‘Failed to assign pinout’ error
- How to use the timing constraints generated by Exostiv Dashboard for Intel?
- Can I use optical SFP cables?
- How to prevent Synplify from changing the net names?
- What is ‘Number of pipes’ in the Capture Configuration of EXOSTIV IP?
- How do I send a cross-capture unit trigger?
- What is the ‘event counter’ and how do I use it?
- Can I rename the probed signals?
- RTL IP core insertion limitations
- Using ‘Design Checkpoint’ (DCP) flow type
- Which FPGA devices are supported?
- How is EXOSTIV IP set up and generated?
- How much FPGA resources does Exostiv IP consume?
- How many FPGA nodes can I connect to EXOSTIV IP?
- Can I use Synplify instead of the FPGA vendor synthesis tool?
- Can I probe multiple clock domains?
- Why do I get an ‘overflow’?
- Can the EXOSTIV Probe provide the transceiver clock?
- What is ‘Storage Qualification’?
- EXOSTIV Probe cannot connect to the target design. What now?
- How can I easily wire my IP throughout hierarchy in RTL flow?
- How do I remove EXOSTIV IP from my netlist to restart insertion?
- How many nodes can I sample continuously without creating overflows?
- Can I share transceiver resources between EXOSTIV IP and the design?
- Is EXOSTIV Dashboard always backward compatible with an IP generated with an older version?
- How do I update the MICA board configuration?
