EXOSTIV is there – and it is not a monster
As you might have noticed, EXOSTIV for Xilinx is now released. With the launch, I have been on the roads to demonstrate the product.
The good thing about meeting FPGA engineers is the flurry of questions, ideas and suggestions received as I show the product. Your feedback helps us find new ideas, find where the most acute pains are and understand what you actually do. I would like to thank you, who have already dedicated some time from your supercharged week to see the product in action. (If you are interested to see the product, please contact me to check our scheduled events with me).
What is EXOSTIV?
Here is one of the slides I use to present EXOSTIV (click here for the complete presentation in PDF):
EXOSTIV is not an emulator.
Why is it important?
Well, because it is sometimes expected from EXOSTIV to be everything at once. Some examples:
– Can it partition design onto multiple FPGA?
(Nope, that’s the role of a partitioning tool. We have to define how our IP can be used with such tools, though).
– Can it implement this (specific) trigger condition?
(Well, some of them, some not. But with it capture capacity, you might not need such a complex trigger).
– Will it be able to replace a protocol analyzer?
(It depends on the protocol and where it is observed…).
Of course, some of your suggested additional features are already in the development pipe at Exostiv Labs… But not all of them.
EXOSTIV’s main value is in the level of visibility it provides for systems running at speed.
New features will be built around this value
Ask yourself: what can you do with 8GB of captured data flowing out of your FPGA at multi-gigabit speed? Would it add something to the flow that your current tools cannot achieve?
At Exostiv Labs, we believe that a tool that tries to be everything at once would probably be very good at nothing, not well fitted to your flow and much too expensive for the value.
EXOSTIV is not such a monster.
Thank you for reading – and Happy Halloween to all!