About: Frederic
Profile:
Posts by Frederic:
- 10 things you should know before SoC Validation (March 20, 2023 - Uncategorized)
- What do you use FPGA prototyping for? (February 17, 2023 - Analysis)
- FPGA prototyping with massive visibility is the key to successful validation (February 17, 2023 - Uncategorized)
- What are the key features of ideal ASIC prototypes? (February 1, 2023 - Analysis)
- RTL or Netlist flow? (April 27, 2022 - Uncategorized)
- What can Exostiv Blade do for FPGA prototyping? (March 17, 2022 - Uncategorized)
- Delivering High Quality Semiconductor IP with confidence (February 9, 2022 - Analysis, Uncategorized)
- Exostiv Blade – Managing Multiple sites, targets and users (December 16, 2021 - Uncategorized)
- Is FPGA Prototyping really optional? (October 25, 2021 - Analysis)
- Upgrading FPGA Prototyping for High RTL Debug Productivity (October 7, 2021 - Analysis)
- Exostiv Blade is a Game Changer (August 10, 2021 - Uncategorized)
- Exostiv Blade – Core capabilities demonstration (July 1, 2021 - Uncategorized)
- Exostiv Blade – Scalable visibility from anywhere (June 7, 2021 - Uncategorized)
- Exostiv – Video Compilation (May 26, 2021 - Uncategorized)
- Exostiv boosts RTL simulation (May 20, 2021 - Uncategorized)
- ASIC designers and FPGA OEMs (May 13, 2021 - Uncategorized)
- Why observability matters (May 10, 2021 - Uncategorized)
- The future of FPGA (May 6, 2021 - Uncategorized)
- White Paper – Why we should scale FPGA tools (May 5, 2021 - Uncategorized)
- Record FPGA data during 1 hour – really (May 5, 2021 - Uncategorized)
- Exostiv – Part 3 – Analyzer Demonstration (April 29, 2021 - Uncategorized)
- Exostiv – Part 2 – Core Inserter Demonstration (April 26, 2021 - Uncategorized)
- Exostiv – Part 1 – Presentation (April 23, 2021 - Uncategorized)
- Massive Real-Time FPGA Data Capture – On-demand Recorded Webinar (April 21, 2021 - Uncategorized)
- You can capture tons of data. Now what? (April 11, 2021 - Uncategorized)
- The FPGA problem we are trying to solve (April 3, 2021 - Uncategorized)
- Did you know that Exostiv can send triggers across clock domains? (March 16, 2021 - Uncategorized)
- Our waveform viewer is 10x faster (December 4, 2020 - Product)
- White Paper – Choosing the ideal FPGA prototype for ASIC and SoC design (December 3, 2020 - Analysis)
- 10 cool things about us… (September 16, 2020 - Company information)
- FPGA prototyping platform gets visibility with EXOSTIV (June 19, 2020 - Uncategorized)
- The FPGA Prototyping problem we are trying to solve (May 31, 2020 - Analysis, Company information, Product)
- How to capture gigabytes of traces from FPGA. At speed. (April 24, 2020 - Analysis, Product)
- EXOSTIV lets you peer deeper into FPGA (April 4, 2020 - Product)
- Record 8GB from a running FPGA – really (May 3, 2019 - Uncategorized)
- Pick a FPGA board, please (January 9, 2019 - Uncategorized)
- Exostiv supports Intel Stratix 10 FPGA (April 18, 2018 - Uncategorized)
- Deep Trace & Bandwidth (August 14, 2017 - Uncategorized)
- Exostiv for Intel (Altera) FPGA – announcement (October 25, 2016 - Uncategorized)
- Debug with reduced footprint (September 8, 2016 - Uncategorized)
- Debugging FPGAs at full speed (April 12, 2016 - Uncategorized)
- EXOSTIV is there – and it is not a monster (October 29, 2015 - Uncategorized)
- ‘My FPGA debug and verification flow should be improved…’ (September 25, 2015 - Uncategorized)
- Does FPGA use define verification and debug? (August 20, 2015 - Analysis)
- Defining targets (for FPGA debug) (March 11, 2015 - Uncategorized)
