Solutions

Exostiv Labs provides the target-agnostic FPGA visibility infrastructure
for verification – from 100,000 x JTAG at speed, on any board.

Exostiv Labs addresses the needs of emerging players building custom AI & RISC-V silicon or complex SoC, IP and FPGA on a focused budget.

If your current verification & validation process is killing your chances of grabbing your market window, our solutions are for you.

Don’t let your system fail in the real world

For teams building SoC, FPGA and IPs tested at 500 MHz+ in a realistic environment over gazillions cycles.
When ‘just simulate harder’ is not the answer.

What’s the issue?

Some bugs only appear at-speed, with real software, on real interfaces.

Simulation says it works. FPGA says it works 30 seconds, then misbehaves. JTAG can’t capture enough.

How do you win?

You can’t throw more compute at simulation and just hope corner cases surface. You need a powerful visibility layer that adapts to your FPGA board – that’s Exostiv.

Don’t debug through a keyhole

For teams designing high-end FPGAs & programmable chips or using them to prototype ASIC that cannot be debugged with a JTAG-based solution.

What’s the issue?

JTAG-based capture limits your view to a few kilobytes forcing frequent system restart and tedious iterations.

You are wasting a lot of time with an inefficient process, and you are destroying your forecasts.

How do you win?

Exostiv Labs lets you capture up to terabytes at speed of operation, and enables system observation over realistic times.

Get emulator visibility at FPGA price

For teams building large chips lacking an emulator. Emulation costs 5-10x – FPGAs run at near-target speed.

What’s the issue?

You cannot afford emulators and you need to hit your tape-out target for a new gen chip – or miss your market window. You need FPGA speed and you have to master the complexity of your system.

How do you win?

Exostiv Labs adds emulation-class visibility to FPGA-class speed and cost.

You are able to reach millions nodes at operating speed.

You are able to build the FPGA prototyping system that’s the closest to your system on a focused budget with the highest performance.

Exostiv’s impact on using FPGA for verification and validation

The chart below explains the impact of Exostiv Labs’ visibility infrastructure on FPGA prototyping used for validation.
Traditionally, FPGA prototypes are used for verification and validation when it is impossible to use simulation any longer: either the system must be tested in realistic conditions (such as when software has to be run) or the events that must be analyzed are beyond the reach of simulation.

In this process, the lack of visibility (and often, the turnaround time) of FPGA boards seriously limits the efficiency of running tests on live systems. Engineers often do more simulations even for long runs – and this, despite impracticable execution times.
In some instances, the lack of visibility infrastructure (or using only standard JTAG tools) makes FPGA prototyping unusable for V & V.

Simulation alone proves to be highly inefficient, with engineers waiting countless hours to simulate just a few milliseconds, when they really need extended – and ‘real-world’ times of operation.

Exostiv Labs visibility infrastructure changes everything. It ‘pushes’ FPGA prototypes beyond its usual area of operation by providing simulation-like visibility in systems running in real-time. Additionnally, with its multi-level instrumentation and ECO mode, ultra fast FPGA turnaround times are within reach.

Success Stories

# 1 Large Soc design with critical communication interface IP

Case:

  • A large SoC design with communication interfaces
  • An interface IP is designed
  • The communication protocol must be tested as compatible with existig peripherals
  • Simulation is not realistic: real world peripherals are not well modelled

Reason for using Exostiv:

  • Only tool capable of capturing large data streams at speed of operation from custom FPGA prototypes.

# 2 RISC processor IP

Case:

  • A RISC processor IP is checked in hardware for proper software execution
  • The is a need to capture software execution at bit level from the running IP and re-build software from waveforms

Reason for using Exostiv:

  • Work with proprietary FPGA board
  • Capture massive data deep inside FPGA at speed of operation
  • Automate captures and testing (Python)

# 3 Radio communications

Cases:

  • Companies building products for radio communication, telecommunications or RADAR
  • The technology is based on FPGA or FPGA is used for prototyping before an ASIC is designed
  • Communications from diverse sources and destinations, satellite, vehicles, networking, mil com…
  • Issue: the modelling of the radio (analog) signal is hard
  • Processing happens in digital domain after A/D conversion et demodulation
  • The resulting data is very large

Reason for using Exostiv:

  • Work with proprietary FPGA board
  • Capture digital domain signal
  • Massively capture digital samples at all taps of digital filters

# 4 Video processing

Cases:

  • Digital video processing in FPGA
  • Data sets are too large for JTAG tools – video typically requires extended history capture
  • Need to capture root causes after hours of testing: cause is far from bug observation

Reason for using Exostiv:

  • Work with proprietary FPGA board
  • Capture massive data deep inside the FPGA prototype at speed of operation
  • Automate captures, testing and processing, with image reconstruction (Python)

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