EXOSTIV
Test, Verify and Debug FPGA
Gigabyte-range visibility into the FPGA at full speed
EXOSTIV is an innovative test, verification and debug solution for FPGA.
It mobilize the FPGA resources to provide really actionable visibility that scales with the complexity of advanced FPGA chips.
EXOSTIV cuts the debug and analysis time from months to weeks and lets you avoid bug escapes to production.
Schedule a DemoBenefits:
- Huge cost savings: no FPGA bugs in production
- Lower total engineering costs
- Allows at speed analysis of complex FPGA design placed in real environment
- Overcomes incomplete or flawed simulation-only approaches
- Adapts to any prototyping board
Reach.
EXOSTIV IP uses the MGTs (Multi-Gigabit Transceivers) to flow captured data out of the FPGA to an external memory. EXOSTIV IP supports repeating captures of up to 32,768 internal nodes simultaneously at the FPGA’s speed of operation (16 data sets x 2,048 bits*).
EXOSTIV IP provides dynamic multiplexer controls to capture even more data sets without the need to recompile. Dynamic ON/OFF controls of data sets let you select the data set and preserve the MGT’s bandwidth for when deeper captures of a reduced set of data is required.
Unlike traditional embedded instruments, the whole debug trace must not be stored inside the FPGA memory. EXOSTIV’s flexible IP structure lets you reach FPGA nodes during long operating times while preserving the memory resources.
*The actual reach depends on the FPGA resources available for debug.
Store.
EXOSTIV Probe provides up to 8 Gigabyte memory to receive and store data captured from the FPGA. This USB 3.0 Super Speed device establishes the communication channel between the EXOSTIV Application and the IP. EXOSTIV Probe provides multiple physical connection types with the target board that holds the FPGA under test. From 1 to 4 Gigabit Transceivers (up to 12.5 Gbps each) can be used over either SFP/SFP+ or HDMI connectors and cables.
EXOSTIV Probe implements a large & high-throughput memory storage located outside the target FPGA. This capability is key to enabling FPGA debugging scenarios that provide up to 200,000 times more observability than approaches that use the FPGA internal memory only.
Analyze.
EXOSTIV Dashboard is composed of the Core Inserter and the Analyzer.
EXOSTIV Core Inserter manages sets up the configuration IP and inserts it at RTL or synthesis level into the design. To do this, it establishes a communication link with the FPGA vendor tool suite.
EXOSTIV Analyzer manages data captures from the target design. It provides tools and controls to view, analyze and export the captured data. EXOSTIV Analyzer includes MYRIAD, the industry’s first waveform viewer capable of handling terabytes of waveform data.
EXOSTIV Dashboard provides the essential controls and tools to speed up debugging session on FPGA in operation. The included MYRIAD waveform viewer provides the key capability to process and visualize very large waveform databases.
