FPGA Debug Reloaded.



In-lab FPGA debug has hit the wall of complexity

FPGA programmability has traditionally enabled engineers to use board prototypes in the lab for debug and verification. Using a system at speed in its ‘real’ environment is used to overcome modeling errors and excessive simulation times.

However, with the unprecedented complexities reached by FPGAs today, usual instrumentation-based methodologies hardly provide sufficient visibility on system-under-test and create tough board implementation constraints.

‘The electronic engineer is like a doctor without X-Ray’

Board bring-up is especially critical. When the FPGA engineer puts the system together, virtually anything can go wrong. The system behavior is ’emergent’, as it is function of not just the individual little pieces, but the way the collectively interact as a whole.

EXOSTIV™ multiplies FPGA visibility by 200,000 !

EXOSTIV™ is a new kind of embedded instrumentation used in the lab at ‘board bring-up’. It provides up to 200,000 times more visibility on the system under test than traditional instrumentation techniques. Unlike software-based techniques and emulation, EXOSTIV™ is used on the target or prototyping boards running at speed of operation. It provides an extended visibility on internal nodes over large periods of time – and this, with a minimal impact on the FPGA resources.

Example of observability of EXOSTIV vs. traditional embedded instrumentation

Why traditional approaches fail

A typical on-board debugging scenario requires finding the roots of a random bug happening once in a while. It may be once every 2 hours or every 3 days.
In such a case, simulation as a sole methodology is impracticable. Furthermore, if simulation has not helped finding the bug earlier, it probably means that there is a model issue in the simulation environment.

Consequently, the FPGA engineer typically uses one of the 2 following type of tools: a logic analyzer or an embedded logic analyzer:

Traditional vs. Embedded Logic Analyzer for FPGA debugging

Choosing one of these techniques results in a trade-off between using a large number of FPGA I/Os and using a large amount of memory inside the FPGA.

By providing extreme FPGA visibility at speed, EXOSTIV™ helps you tackle the toughest debug & verification challenges.

Logic Analyzer Embedded LA EXOSTIV™
Observable nodes Typ. 64 to 128
Impacts nr of FPGA I/Os

Up to 16 x 2,048

Capture depth Megabyte Kilobyte
Impacts FPGA memory


Sampling speed Limited by I/Os speed
& board routing
At FPGA speed

At FPGA speed

Open a new range of debugging scenarios

EXOSTIV™ is composed of a configurable IP, a hardware probe and a software application.

EXOSTIV™ uses the FPGA’s gigabit transceivers to flow captured data to an external memory, providing up to 8 Gigabyte of external data storage for debug traces.

EXOSTIV enables new FPGA debugging scenarios

Unprecedented observable FPGA operating times

With EXOSTIV™, extended operating times of ‘live FPGA’ can now be observed – as a single capture or as a series of repeating bursts.

EXOSTIV™ is the ideal companion to simulation for identifying the potential modeling issues and capturing specific and extended logic sequences that can be reused in simulation to verify design.

Minimal constraints in FPGA and on board

EXOSTIV™ IP’s footprint is similar to this of traditional embedded instrumentation IPs – except that the required memory resources do not grow with larger capture needs.
IP structure enhancements provide lots of flexibility for defining triggers at run-time and selecting data groups, thereby reducing the need to repeat FPGA implementation.

EXOSTIV™ provides two connecting solutions (HDMI & SFP) & additional adapters.

No learning curve

EXOSTIV™ connects to the FPGA vendor’s synthesis and implementation software to insert EXOSTIV IP after synthesis (netlist level). The debug flow defined for EXOSTIV is identical to this of traditional embedded logic analyzer.

Very large databases capture & analysis

EXOSTIV™ Dashboard Application includes the controls for defining rich triggers and data qualification conditions. It provides the control for setting up and running captures – and integrates MYRIAD™, the first waveform viewer capable of handling terabytes of waves.

Check EXOSTIV™ technical specifications – EXOSTIV for Xilinx FPGA / EXOSTIV for Intel FPGA

EXOSTIV enables new FPGA debugging scenarios


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