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AMD FPGA: which files are produced in RTL flow and how do I use them?

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AMD FPGA: which files are produced in RTL flow and how do I use them?

Applies to IP generated with Exostiv Dashboard targeting AMD devices.

For Exostiv Core Inserter (software v2) and for Exostiv Dashboard from version 1.11.0 (software v1):

  • <instance name>.edf (1) : EXOSTIV IP synthesized netlist.
  • <instance name>_pkg.vhd (2) : VHDL package containing the types used for the EXOSTIV IP instantiation.
  • <instance name>_module.v (3) : Verilog module for EXOSTIV IP netlist
  • <instance name>_pinout.xdc (4) : Constraint file for EXOSTIV IP pinout. (like transceivers location).
  • <instance name>_wrapper.xdc (5) : Constraint file with the timing constraints of EXOSTIV IP.
  • <instance name>.vho : Example template on how to create a VHDL instance of EXOSTIV IP in the target design.
  • <instance name>.vo : Example template on how to create a Verilog instance of EXOSTIV IP in the target design.

(1) Add to Vivado project for synthesis / P&R in VHDL or Verilog flow.
(2) Add to Vivado project for synthesis / P&R in VHDL flow.
(3) Add to Vivado project for synthesis / P&R in Verilog flow.
(4) Add to Vivado project for synthesis / P&R in VHDL or Verilog flow.
(5) Add to Vivado project but do not use for synthesis. You have to ‘scope’ this file on the Exostiv IP wrapper. Here are the commands:
Case 1: project mode:
add_files -fileset constrs_1 -norecurse <file_path>/<instance_name>_wrapper.xdc
set_property SCOPED_TO_REF <instance name>_wrapper [get_files <file_path>/<instance_name>_wrapper.xdc]
set_property used_in_synthesis false [get_files <file_path>/<instance_name>_wrapper.xdc]

Case 2: non-project mode:
read_xdc -ref <instance name>_wrapper <file_path>/<instance_name>_wrapper.xdc
set_property used_in_synthesis false [get_files <file_path>/<instance_name>_wrapper.xdc]

Exostiv Dashboard older than 1.11.0:

  • <instance name>.edf(1) : EXOSTIV IP synthesized netlist.
  • <instance name>_pkg.vhd(2) : VHDL package containing the types used for the EXOSTIV IP instantiation.
  • <instance name>_module.v(3) : Verilog module for EXOSTIV IP netlist
  • <instance name>_timing.tcl(4) : Constraint file with the timing constraints of EXOSTIV IP.
  • <instance name>_pinout.xdc(5) : Constraint file for EXOSTIV IP pinout. (like transceivers location).
  • <instance name>.vho : Example template on how to create a VHDL instance of EXOSTIV IP in the target design.
  • <instance name>.vo : Example template on how to create a Verilog instance of EXOSTIV IP in the target design.

(1) Add to Vivado project for synthesis / P&R in VHDL or Verilog flow
(2) Add to Vivado project for synthesis / P&R in VHDL flow
(3) Add to Vivado project for synthesis / P&R in Verilog flow
(4) This file must be sourced in the project between synthesis and implementation: “source -notrace <instance name>_timing.tcl”
(5) Add to Vivado project for synthesis / P&R in VHDL or Verilog flow – OR – source it between synthesis and implementation.

Depending on whether you use Vivado interactively with the GUI or with a full set of scripts, using the above set of files can prove a little complex. It is especially the case when using the GUI: Vivado repeatedly prompts for saving – and knowing what to do might not be obvious. Specifically, when existing synthesis results are modified, Vivado used in GUI mode automatically assumes the project has been updated and then requires the synthesis to be run again. There are ways to avoid this – please follow these guidelines:

Case 1: step by step interactive Vivado usage with the GUI:
Our constrains are applied using a TCL script, not using standard XDC file.
The additional constraints provided for the Exostiv IP should be applied to an opened synthesized database but should not be saved in a XDC file.
To do this:
1) Synthesize your design with the Exostiv IP source files;
2) Open the synthesized design;
3) Source the timing constraint file generated with the Exostiv IP;
4) Keep the synthesized design open; do NOT save anything;
5) Run the implementation (answer NO if Vivado asks for saving the design before running the implementation);
6) Run the bitstream file generation (answer NO if Vivado asks for saving the design before running bitgen);
7) When it is done, you can close the synthesized design without saving the modifications to the constraints.

Case 2: edit and run a script
Click here to download a reference script template.
Edit the file path and names in the script to match your project settings.
Save script to scriptname.tcl.
a) Open a Vivado TCL shell window
b) Run script: source -notrace /scriptname.tcl

Please note: this solution supposes that you have previously created a Vivado project file (.XPR file) with all HDL sources and XDC files.

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