Applies to IP generated with Exostiv Dashboard targeting AMD devices, except Versal devices
For AMD Versal devices, please refer to the following article: AMD Versal: insertion flows overview.

For Exostiv Core Inserter (software v2)

• <instance name>_wrapper.edf (1) : EXOSTIV IP synthesized netlist.
• <instance name>_wrapper_pkg.vhd (2) : VHDL package containing the types used for the EXOSTIV IP instantiation.
• <instance name>_wrapper_module.v (3) : Verilog module for EXOSTIV IP netlist
• <instance name>_wrapper_pinout.xdc (4) : Constraint file for EXOSTIV IP pinout. (like transceivers location).
• <instance name>_wrapper.xdc (5) : Constraint file with the timing constraints of EXOSTIV IP.
• <instance name>_wrapper.vho : Example template on how to create a VHDL instance of EXOSTIV IP in the target design.
• <instance name>_wrapper.vo : Example template on how to create a Verilog instance of EXOSTIV IP in the target design.

(1) Add to Vivado project for synthesis / P&R in VHDL or Verilog flow.
(2) Add to Vivado project for synthesis / P&R in VHDL flow.
(3) Add to Vivado project for synthesis / P&R in Verilog flow.
(4) Add to Vivado project for synthesis / P&R in VHDL or Verilog flow.
(5) Add to Vivado project but do not use for synthesis. You have to ‘scope’ this file on the Exostiv IP wrapper. Here are the commands:
— Case 1: project mode:
add_files -fileset constrs_1 -norecurse <file_path>/<instance_name>_wrapper.xdc
set_property SCOPED_TO_REF <instance name>_wrapper [get_files <file_path>/<instance_name>_wrapper.xdc]
set_property used_in_synthesis false [get_files <file_path>/<instance_name>_wrapper.xdc]

— Case 2: non-project mode:
read_xdc -ref <instance name>_wrapper <file_path>/<instance_name>_wrapper.xdc
set_property used_in_synthesis false [get_files <file_path>/<instance_name>_wrapper.xdc]