Visibility into the FPGA.
Knowledgebase
11 Articles Bundles and licensing
- Can I activate the license through a proxy?
- I cannot lease a floating license in Debian 9 / Debian Stretch
- What is the software build number and how can I check it?
- I cannot activate my license online. What now?
- Can I install EXOSTIV Dashboard in a Virtual Machine?
- Can I upgrade my Probe?
- How do I activate my license?
- Which date is taken into account for my license subscription?
- Where can I find my license key?
- What kind of licensing is available?
22 Articles Software installation
- EXOSTIV Dashboard for Xilinx – Release Notes
- EXOSTIV Dashboard for Intel – Release Notes
- Windows cannot install the driver automatically. What now?
- Probe firmware update
- Is MacOS supported?
- Can I activate the license through a proxy?
- How to use libusb without administrator privileges?
- What is the software build number and how can I check it?
- Vivado does not start anymore after installing the latest version of Exostiv Dashboard. What happened?
- Should I use Linux or Windows for best software performance?
21 Articles EXOSTIV Probe
- Once in a while, the Probe disconnects from the PC. What happened?
- I cannot connect to the probe over USB
- Windows cannot install the driver automatically. What now?
- The front panel LED is blinking on EXOSTIV Probe. What does it mean?
- Probe firmware update
- How do I match transceivers on my board with these on the probe?
- Can I use optical SFP cables?
- Can I generate any output frequency on the probe’s ‘clock out’ connector?
- Does EXOSTIV support ASIC / SoC prototyping systems?
- What is the maximum capture length for EXOSTIV?
24 Articles EXOSTIV IP
- What is ‘Number of pipes’ in the Capture Configuration of EXOSTIV IP?
- Which files are produced in RTL flow and how do I use them?
- ‘Failed to assign pinout’ error
- How to use the timing constraints generated by Exostiv Dashboard for Intel?
- Can I use optical SFP cables?
- How to prevent Synplify from changing the net names?
- RTL IP core insertion limitations
- Using ‘Design Checkpoint’ (DCP) flow type
- Which FPGA devices are supported?
- How is EXOSTIV IP set up and generated?
29 Articles Core Inserter
- Which files are produced in RTL flow and how do I use them?
- ‘Failed to assign pinout’ error
- How to use the timing constraints generated by Exostiv Dashboard for Intel?
- My version of Linux does not support libusb. Can I still use the Core Inserter?
- Can I run Vivado and Exostiv Dashboard on separate machines for netlist core insertion?
- What is ‘Number of pipes’ in the Capture Configuration of EXOSTIV IP?
- What is the software build number and how can I check it?
- RTL IP core insertion limitations
- Using ‘Design Checkpoint’ (DCP) flow type
- Where can I find a video showing how to use Exostiv Dashboard?
21 Articles Analyzer
- What is the maximum capture length for EXOSTIV?
- How to use libusb without administrator privileges?
- What is the software build number and how can I check it?
- EXOSTIV waves ‘binary format’ description
- Can I export the waves to a non-native format automatically?
- Where can I find a video showing how to use Exostiv Dashboard?
- Which FPGA devices are supported?
- Which OS is supported?
- What is the difference between ‘Burst to Probe’ and ‘Stream to Probe’?
- Does EXOSTIV provide sequential trigger?
10 Articles Waveform Viewer
- Should I use Linux or Windows for best software performance?
- EXOSTIV waves ‘binary format’ description
- Can I export the waves to a non-native format automatically?
- What is the maximum capture length for EXOSTIV?
- The cursors marking the trigger have disappeared. What happened?
- Where can I find a video showing how to use Exostiv Dashboard?
- Can I probe multiple clock domains?
- Can we export the waves?
- How do I run multiple capture units simultaneously?
- Can I display waves from multiple clock domains in the same waveform window?
2 Articles Accessories
33 Articles Troubleshooting
- Can I generate any output frequency on the probe’s ‘clock out’ connector?
- Once in a while, the Probe disconnects from the PC. What happened?
- Vivado DRC error – PLDS-1 rule violation encountered. What does this mean?
- How to prevent Synplify from changing the net names?
- I received an unexpected overflow error with a burst size smaller than 256 or 512 samples. What happens?
- Can I activate the license through a proxy?
- EXOSTIV Dashboard for Xilinx – Release Notes
- I cannot lease a floating license in Debian 9 / Debian Stretch
- EXOSTIV Dashboard for Intel – Release Notes
- How to use libusb without administrator privileges?
16 Articles Miscellaneous
- Does EXOSTIV support ASIC / SoC prototyping systems?
- How to prevent Synplify from changing the net names?
- Probe firmware update
- Is MacOS supported?
- What is the maximum capture length for EXOSTIV?
- Can I activate the license through a proxy?
- What is the software build number and how can I check it?
- Should I use Linux or Windows for best software performance?
- My version of Linux does not support libusb. Can I still use the Core Inserter?
- How do I match transceivers on my board with these on the probe?
