Benefits:

• Lower total engineering costs
• Allows at speed analysis of complex FPGA design placed in real environment
• Overcomes incomplete or flawed simulation-only approaches
• Adapts to any prototyping board
• Huge cost savings: no FPGA bugs in production

Connectivity

Download connecting guide (PDF).

Exostiv Probe EP16000 connects to FPGA chips transceivers, supporting up to 4 transceivers at 16.25 Gbps each (up to 65 Gbps per connector). EP28000 uses up to 4 transceivers at 28.125 Gbps each (up to 112.5 Gbps per connector).

Exostiv Probe front panel provides 2 type connector types:
– QSFP28, compatible connectivity such as QSFP+, SFP28 or SFP+ with adapters are supported.
– SAMTEC ARF-6. This solution offers a small footprint connectivity solution for boards where space is limited. Cable reference part number: ARC6-08-xx.x-LU-LD-2-1.

Standard IP

Main features include:

• Multiple capture unit with distinct sampling clock source
• Sampling up to 800 MHz
• Up to 16 x 2K bits simult. sampling per IP core instance
• Multiple data groups with dynamic selection at runtime
• Cross-clock domain triggering and data qualification
• Trigger positioning across the whole Exostiv Probe capture memory
• BRAM-based and Streaming (DDR based) modes of captures

Extended width IP

Main features include:

• Multiple capture units with distinct sampling clock source
• Sampling up to 109 MHz
• Up to 65K bits simult. sampling per IP core instance
• Extremely small footprint.
• Triggering on up to 2,048 inputs
• Trigger positioning across the whole Exostiv Probe capture memory
• Streaming (DDR based) mode of capture

IP insertion flows

Exostiv core inserter enables IP generation, insertion and modification at 3 levels:

• RTL level: Exostiv IP instances are generated as a synthesized netlist with a VHDL or Verilog wrapper, design constraints and insertion template. The IP is inserted into the target design by the user like any other part of the design. Afterwards, the whole design has to be synthesized and implemented by the user. This mode of insertion provides full control to the user for insertion in the source code.
• Netlist level: (AMD FPGA only) Prior to proceeding with this type of insertion, the user has to load a post-synthesis design checkpoint in the FPGA vendor tool. Exostiv Core Inserter interacts with the vendor tool to select the sampling clock signals and the nodes to be observed with the Exostiv IP instance. Thereafter, Exostiv IP instances are synthesized and automatically inserted into the target design netlist. This is followed by automatic or manual implementation (P&R) and bitstream generation.
• ECO (Engineering Change Order – AMD FPGA only): This special level enables late modifications of the connections between a specific IP instance and the design under test. Prior to proceeding with it, the user has to load a post place and route DCP into the vendor tool. Exostiv core inserter interacts with the vendor tool to modify the existing connections with the FPGA under test. When the Exostiv IP resources need not to be modified, this mode provides the fastests turnaround time to observe new sets of FPGA nodes.