Visibility into the FPGA.

Can I probe multiple clock domains?

Can I probe multiple clock domains?

Yes: this requires using a distinct capture unit for each clock domain.

EXOSTIV IP is a synchronous IP that works in a sampling scheme. It is divided into up to 16 capture units – basically logic units in charge for sampling nodes from the target FPGA and send the samples to the EXOSTIV IP Probe external memory.
Each capture unit uses a sampling clock for capturing data samples. Hence you can capture data from up to 16 different clock domains with the same EXOSTIV IP.
If it is required to watch events occurring in multiple clock domains, the FPGA nodes to be observed should be grouped by clock domain. At least one capture unit should be defined by clock domain (you can define more than one capture unit per clock domain).
In EXOSTIV Analyzer, there is one control tab per capture unit. The captures of each capture unit will be displayed in the corresponding waveform window.

*** Bonus ***
An interesting feature of EXOSTIV IP is the ability to send a trigger from any capture unit to any capture unit. As a result, you can start capturing data in one clock domain from an event detected in another clock domain.