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Intel FPGA: which files are produced in RTL flow and how do I use them?

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Intel FPGA: which files are produced in RTL flow and how do I use them?

Applies to Exostiv Dashboard for Intel

  • <instance name>_pinout.tcl. Assigns the additional pins required with EXOSTIV IP.
  • <instance name>_sources.tcl. Adds the required source files to the Quartus project for use with EXOSTIV IP

1) Please open the file <instance name>_sources.tcl with a text editor and follow the instructions about ‘relative paths’ and .qdb partitioning (qdb partitioning only applies when Quartus Prime PRO is used). The instructions are enclosed in the comments in these files.
2) Please source the 2 above tcl scripts in your .qsf project file. Please make sure to use relative path when referencing the scripts:
Add the following lines to the project .qsf file:
>> source <relative_path>/exi_top_pinout.tcl
>> source <relative_path>/exi_top_sources.tcl
– Example: (click here to download a full .qsf file example – check lines 125 and 126)
source “../../test/IP184-4ch/exi_top_pinout.tcl”
source “../../test/IP184-4ch/exi_top_sources.tcl”
An example of .qsf file is also provided (Sample.qsf).

Please find the list of generated files with their description below:

  • <instance name>.qxp : EXOSTIV IP synthesized netlist.
  • <instance name>_wrapper.vhd : EXOSTIV IP top level wrapper. This module must be instantiated in the target design.
  • <instance name>_wrapper.vho : Example template on how to create a VHDL instance of EXOSTIV IP in the target design.
  • <instance name>_wrapper.vo : Example template on how to create a Verilog instance of EXOSTIV IP in the target design.
  • <instance name>_pinout.tcl : Script containing the pinout constraints required by the EXOSTIV IP
  • <instance name>_timing.sdc : Constraint file with the timing constraints of EXOSTIV IP.
  • <instance name>_wrapper_pkg.vhd : VHDL package containing the types used for the EXOSTIV IP instantiation.
  • <instance name>_wrapper_module.v : Verilog module for EXOSTIV IP netlist.
  • <instance name>.vhd : VHDL entity for EXOTIV IP netlist
  • sample.qsf : Example of required TCL commands to insert at the end of QSF file, to add the Exostiv IP to the Quartus project.
  • exi_sync_reset.vhd : Internal source file for EXOSTIV IP.
  • exi_xcvr_startup_clock.vhd : Internal source file for EXOSTIV IP.
  • exi_xcvr_top.vhd : Internal source file for EXOSTIV IP.

For Quartus Standard Edition:

  • <instance name>.qxp : EXOSTIV IP synthesized netlist.
  • exi_refclk_div.qsys : Internal file for EXOSTIV IP.
  • exi_xcvr_fpll.qsys : Internal file for EXOSTIV IP.
  • exi_xcvr_atxpll.qsys : Internal file for EXOSTIV IP.
  • exi_xcvr_rst.qsys : Internal file for EXOSTIV IP.
  • exi_xcvr_rx.qsys : Internal file for EXOSTIV IP.
  • exi_xcvr_tx.qsys : Internal file for EXOSTIV IP.

For Quartus Pro Edition:

  • <instance name>.qdb : EXOSTIV IP synthesized netlist.
  • exi_refclk_div.ip : Internal file for EXOSTIV IP.
  • exi_xcvr_fpll.ip : Internal file for EXOSTIV IP.
  • exi_xcvr_atxpll.ip : Internal file for EXOSTIV IP.
  • exi_xcvr_rst.ip : Internal file for EXOSTIV IP.
  • exi_xcvr_rx.ip : Internal file for EXOSTIV IP.
  • exi_xcvr_tx.ip : Internal file for EXOSTIV IP.
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