Exostiv Blade – Scalable visibility from anywhere
You might have heard about Exostiv Blade already.
From the outside, a lot in this product appears to be a massive scale up of EXOSTIV. I thas got: more ports, more bandwidth, more memory, multi-FPGA, multi-clock domain. In other words: massive visibility… only more MASSIVE. EXOSTIV targets FPGA OEMs, IP companies and small ASIC. So, Exostiv Blade is for large ASIC / large semiconductor companies as well…?
Right? Well… partly only. Let’s review what is different with Exostiv Blade.
Exostiv Blade is built for remote work from the bottom up.
Its client-server architecture allows remote users to:
- Manage the Exostiv Blade as an appliance on the company network
- Set up test sessions: reserving some of the hardware resources for a specific job
- Capture data live or with queued jobs
- Access and visualize the captured data remotely
- Manage the capture databases
Exostiv Blade enables multi-site, multi-target, multi-user FPGA test infrastructures.
In addition, we can built Exostiv Blade in a variety of chassis to adapt for the test site requirements. For instance, in its simplest configuration, it can sit (silently) on a desk and can be used without network, with a simple point-to-point connection.
Scalable resources & uncompromised performance
Each Exostiv Blade is built according to the user’s needs.
The number of high speed ports and the storage memory are the 2 main parameters. Exostiv Blade provides a lot of flexibility as of the usage of these resources: connecting multiple separate boards, multiple boards of the same prototyping system, multiple FPGA on common or separate boards, … all of this is possible.
Mutltiple users can share the same Exostiv Blade distinct projects. Each would reserve a part of the Exostiv Blade’s hardware resources.
Beyond the choice of the chassis, additional options include functional software packages, and other hardware options – like additional hard disks, RAID and so on…
Standard chassis with available slots. In this example, slot 1 and slot 3 are used.
Exostiv Blade’s architecture requires using FPGA transceivers to extract data at up to 25 Gbps per link; a standard connectivity port includes 4 transceivers in the same target FPGA quad – 100 Gbps max. Each port of the Exostiv Blade communicates with an Exostiv Blade IP located in the target test system FPGAs for data extraction. These IP instances are generated with the Exostiv Blade Core Inserter software, provided separately.
The current ‘standard’ Exostiv Blade model features:
- 4x 100 Gbps inputs ports (max. sustainable data rate).
- 4x 16 GB memory for trace storage (extensible to 4 x 128 GB).
This represents a 8x increase on both the available bandwidth and trace storage compared to Exostiv! The ‘standard’ chassis can currently host up to 3 times these resources. When equipped with the largest available memory (128 GB per 100 Gbps) the fully populated chassis reaches a staggering 24x increase on the total aggregated bandwidth and a 192x increase on the trace memory!
(In a future post, we’ll provide numbers of what this represents in terms of real-time capture from live boards at typical frequencies. Stay tuned.)
Exostiv Blade example configurations
std chassis, min.
std chassis, max.
|50 Gbps||400 Gbps||1,200 Gbps|
|8 GB trace mem||64 GB trace mem||1,536 GB trace mem|
Exostiv vs. Exostiv Blade
|8 GB | 50 Gbps non-scalable||Nx (16 to 128 GB | 100 Gbps) fully scalable (base: N = 4)|
|USB interface||Stand-alone appliance|
|Host-based||Client-server architecture or point to point|
Exostiv Blade is a game changer (to be continued)
In this article, we have wanted to briefly explain the main characteristics of Exostiv Blade.
You might want to see a demonstration of some core capabilities of Exostiv Blade – click here.
In a follow-up post, we’ll talk about the usages of this appliance and how it bridges design debug with pre-production tests of IP, FPGA and ASIC.
Stay with us – we’ll cover why managing your CAPEX & OPEX between emulators, standard and custom prototyping boards (here is an interesting external reference) is getting easier.
Thank you for reading.