Capturing every filter tap: signal processing verification when the analog world won’t fit in a testbench

Tags: At-speed bugs, Capture depth

Context Companies building radio communication, telecommunications and RADAR systems — satellite links, vehicle communications, networking, military communications. FPGA is either the production technology or the prototyping vehicle before an ASIC. The processing chain operates in the digital domain, after A/D conversion and demodulation.

The problem Modelling the analog radio signal in simulation is notoriously hard. The realistic test is the real signal — captured live, through the actual analog front-end. But the resulting digital data is enormous: verifying a filter chain means observing every tap, across long signal sequences, at full sampling rate.

Why standard tools failed The data volume is orders of magnitude beyond what JTAG-based capture can hold. Observing a single tap for a few microseconds tells you nothing about a demodulation issue that emerges over seconds of real signal.

The Exostiv approach Exostiv was deployed on the teams’ proprietary boards, capturing the digital domain signal massively — samples from all taps of the digital filters, simultaneously, at operating speed, over realistic signal durations.

The result The processing chain was verified against real signals instead of imperfect models. Issues invisible in simulation — because the simulated signal was too clean, too short, or simply wrong — were observed and fixed on the prototype.