How a SoC team validated a communication interface that simulation could not model

Tags: At-speed debug, Large Designs.

Context A semiconductor company designing a large SoC with multiple communication interfaces. One interface IP, developed in-house, had to be proven compatible with existing third-party peripherals before tape-out. The prototype ran on a custom FPGA board.

The problem The compatibility could not be verified in simulation: real-world peripherals are poorly modelled, and the relevant behaviors only emerge in interaction with actual devices. The team needed to observe the interface operating against real peripherals, at real speed, over extended periods — exactly the conditions simulation cannot reproduce.

Why standard tools failed JTAG-based capture offered a window of a few kilobytes before forcing a system restart. Interface compatibility issues appear sporadically across long traffic sequences — a few kilobytes of visibility makes catching them a matter of luck, not method.

The Exostiv approach Exostiv was deployed on the team’s custom board — the only solution capable of capturing large data streams at speed of operation from custom FPGA prototypes. The interface was observed in continuous operation against real peripherals, with captures spanning realistic traffic sessions instead of millisecond snapshots.

The result The interface was validated against real peripherals before tape-out. For a design of this size, an interface bug discovered in silicon means a re-spin — typically a high six-figure cost and a 3 to 4-month delay. The validation happened on the prototype, where fixing a bug costs a recompile.