Rebuilding software execution from hardware waveforms on a RISC processor IP

Tags: Capture Depth, Debug automation

Context A processor IP company verifying a RISC core in hardware. The verification requirement: confirm correct software execution at bit level, directly from the running IP — on the company’s proprietary FPGA board.

The problem Verifying software execution in hardware means capturing the processor’s internal state continuously over the full execution — millions of cycles. The captured waveforms then need to be processed to reconstruct the instruction flow and compare it against expected behavior. Any gap in the capture breaks the reconstruction.

Why standard tools failed JTAG-based tools capture kilobytes, then stop. Reconstructing a software execution from fragments separated by system restarts is not reconstruction — it is guesswork. The proprietary board also ruled out any platform-locked debug solution.

The Exostiv approach Exostiv instrumented the core on the proprietary board and captured execution traces deep inside the FPGA, at speed, continuously. The capture and verification flow was automated in Python — captures triggered, retrieved, and post-processed into reconstructed software traces without manual intervention, ready for integration into regression runs.

The result Where JTAG offered kilobytes between restarts, Exostiv delivered gigabytes of continuous execution history in a single session. The reconstruction became deterministic instead of fragmentary, and the automated flow turned a manual debug exercise into a repeatable verification step.