JTAG gives you milliseconds. Your bug appears after minutes.
The buffer fills. The system restarts. The bug disappears. And the cycle begins again.
The scenario you recognize
You know exactly what you are looking for. You set your trigger. You run. ILA fills up in 2 milliseconds — or 20, or 200 — and stops. The system restarts. You adjust the trigger slightly and try again. Hours pass. The bug either doesn’t appear in your capture window, or it does and the context you need to understand it is gone.
This is not an edge case. This is the standard JTAG debug loop. And it is structurally incapable of solving a class of bugs that only exist over time.
The structural limit of JTAG-based tools
Vivado ILA, Intel SignalTap, and similar tools store captured data in FPGA on-chip memory — BRAM. BRAM is shared between your design and your debug infrastructure. The result: a capture window measured in kilobytes, sometimes a few megabytes at most, before the buffer is full and the system must stop.
This is not a software limitation. It is a hardware architecture choice — one that made sense when FPGAs were simpler and designs were smaller. Today’s designs routinely require capture windows that are orders of magnitude beyond what on-chip memory can provide.
What Exostiv does differently
Exostiv routes captured data through FPGA transceivers to external memory — gigabytes, not kilobytes. The design keeps running. The capture keeps recording. You decide when to stop, not the buffer.
The result: a capture window measured in seconds, minutes, or hours. Every event that happened during that window is available for analysis. No restarts. No lost context. No trigger lottery.
The numbers
200,000x more capture depth than JTAG-based tools. Up to 8 GB per Probe unit. Up to terabytes on Blade configurations. One software environment from bench setup to multi-FPGA lab.
See it on your board – Request a demo.
