You can’t fix what you don’t see

By on October 11, 2024   /   Uncategorized  
You can’t fix what you don’t see
You can't fix what you don't see (Download PDF version) Whether you're designing a single IP, an FPGA-based product, a CPU coprocessor, an ASIC, or a System on Chip (SoC), your product must work as intended—ideally flawlessly, though "good enough" often applies. The process starts with aRead more →
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Exostiv boosts RTL simulation

By on May 20, 2021   /   Uncategorized  
Exostiv boosts RTL simulation
Exostiv boosts RTL simulation It is essential to reduce the wasted machine cycles used for simulation workloads. Simulation dominates ASIC/SoC/FPGA verification process 'The 2020 Wilson Research Group ASIC and FPGA Functional Verification Study' reports that an ASIC, SoC or FPGA designer can spend up to 40% ofRead more →
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You can capture tons of data. Now what?

By on April 11, 2021   /   Uncategorized  
You can capture tons of data. Now what?
You can capture tons of data. Now what? Offering huge new capabilities is not always seen positively. Sometimes, engineers come to us and ask: 'Now that I am able to collect Gigabytes of trace data from FPGA running at speed... how do I analyze that much data?'.Read more →
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10 cool things about us…

By on September 16, 2020   /   Company information  
10 cool things about us…
10 cool things about us... #1 Our waveform viewer commonly processes Gigabytes of waves without lagging That's because we have to display data recorded from #FPGA in operation during seconds, minutes or even hours, not just a window of waves from a simulation. So we needed toRead more →
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Does FPGA use define verification and debug?

By on August 20, 2015   /   Analysis  

Does FPGA use define verification and debug? You may be aware that we have run a first survey on FPGA design, debug and verification during the last month. (By the way, many thanks to our respondents – we’ll announce the Amazon Gift Card winner in September). In

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