(This article applies to EXOSTIV for Xilinx.)
When inserting EXOSTIV IP into a FPGA, the following constraints are applicable on the transceiver resources:

1) When using a transceiver for EXOSTIV IP, both Tx and Rx are reserved.
2) If EXOSTIV IP is used at data rates that require using the quad QPLL, this one is unavailable for the rest of the design.
3) If EXOSTIV IP is used at data rates that require using the local link CPLL, the other CPLLs and the QPLL are available for the rest of the design.