You can’t fix what you don’t see

By on October 11, 2024   /   Uncategorized  
You can’t fix what you don’t see
You can't fix what you don't see (Download PDF version) Whether you're designing a single IP, an FPGA-based product, a CPU coprocessor, an ASIC, or a System on Chip (SoC), your product must work as intended—ideally flawlessly, though "good enough" often applies. The process starts with aRead more →
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What do you use FPGA prototyping for?

By on February 17, 2023   /   Analysis  
What do you use FPGA prototyping for?
What do you use FPGA prototyping for? Typical usages of FPGA prototyping FPGA Prototyping is used for various purposes. Here are 2 of its main usages: FPGA Debug: at some point of the FPGA design cycle, tests have to be run with a 'real' FPGA board toRead more →
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Exostiv Blade is a Game Changer

By on August 10, 2021   /   Uncategorized  
Exostiv Blade is a Game Changer
Exostiv Blade is a Game Changer How it started Exostiv Blade all started from client requests in 2018-2019, especially from ASIC & SoC companies. They were seduced by the capture capabilities of Exostiv from FPGA running at speed - in some cases more powerful than the visibilityRead more →
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Why observability matters

By on May 10, 2021   /   Uncategorized  
Why observability matters
Why Observability matters. At Exostiv Labs, we think that 'Observability' - or 'Visibility' - that is 'the ability to observe (and understand) a system from its I/Os' - is relevant - and even key to FPGA debug. I'd like to show it with a real example takenRead more →
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Record FPGA data during 1 hour – really

By on May 5, 2021   /   Uncategorized  
Record FPGA data during 1 hour - really
Record FPGA data during 1 hour - really. As ASIC, SoC and FPGA engineers, we are used to watching the operation of our designs based on single limited snapshots. RTL simulations, for instance, provide bit-level details during execution times that span over a few (milli)seconds at best.Read more →
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Our waveform viewer is 10x faster

By on December 4, 2020   /   Product  
Our waveform viewer is 10x faster
Our new waveform viewer is 10x faster! I am happy to announce that Exostiv Dashboard 1.10.0 has been released this week. In addition to the usual maintenance on supporting new devices, new versions of FPGA tools, and a discreet yet fresh icon set update, this is theRead more →
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EXOSTIV lets you peer deeper into FPGA

By on April 4, 2020   /   Product  
EXOSTIV lets you peer deeper into FPGA
EXOSTIV lets you peer deeper into FPGA Watch now... EXOSTIV Introduction EXOSTIV's structure (see below) allows deeper data capture from inside FPGA: unlike JTAG instrumentation, EXOSTIV provides an external storage that extends beyond the memory available in the FPGA. Coupled with the usage of transceivers, it createsRead more →
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Deep Trace & Bandwidth

By on August 14, 2017   /   Uncategorized  
Deep Trace & Bandwidth
Deep Trace & Bandwidth Exostiv provides the following maximum capabilities for capturing data from inside FPGA running at speed: Capabilities. 50 Gigabit per second bandwidth for collecting FPGA traces. 8 Gigabyte of memory for trace storage. 32,768 nodes probing simultaneously. 524,288 nodes reach. Actually, we have builtRead more →
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Debug with reduced footprint

By on September 8, 2016   /   Uncategorized  
Debug with reduced footprint
Debug with reduced footprint Footprint, 'real estate', resources, ... No matter the design complexity, allocating resources to debugging is something you'll worry about. If you are reading these lines, it is likely that you have some interest in running some of your system debugging from a realRead more →
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Debugging FPGAs at full speed

By on April 12, 2016   /   Uncategorized  
Debugging FPGAs at full speed
Debugging FPGAs at full speed In my previous post, I explained why increasing the available 'window of visibility' is a gigantic advantage when tracking system-level issues on modern complex FPGAs. EXOSTIV's structure does not require the FPGA internal memory to grow with the depth of the capture.Read more →
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Does FPGA use define verification and debug?

By on August 20, 2015   /   Analysis  

Does FPGA use define verification and debug? You may be aware that we have run a first survey on FPGA design, debug and verification during the last month. (By the way, many thanks to our respondents – we’ll announce the Amazon Gift Card winner in September). In

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Defining targets (for FPGA debug)

By on March 11, 2015   /   Uncategorized  
Defining targets (for FPGA debug) I recently attended a technical seminar organized in The Netherlands by one of the major FPGA vendors (hint: it is one of the 2 top vendors among the '4 + now single outsider' players in the very stable FPGA market). During theRead more →
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