EXOSTIV
All articles about EXOSTIV
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Software installation
- Segmentation fault (core dumped) QT_QPA_PLATFORM_PLUGIN_PATH – crash
- FPGA database update package installation
- Installing Exostiv Dashboard Software under Linux
- How do I set up the Exostiv Dashboard client to lease floating licenses from the server?
- How to check the expiration date of my floating license?
- How to check the expiration date of my node-locked license?
- I have a permanent / perpetual license, but I see it has expired. What happened?
- EXOSTIV Dashboard-A – Release Notes
- EXOSTIV Dashboard-I – Release Notes
- Windows cannot install the driver automatically. What now?
- Probe firmware update
- Is MacOS supported?
- Can I activate the license through a proxy?
- How to use libusb without administrator privileges?
- What is the software build number and how can I check it?
- Vivado does not start anymore after installing the latest version of Exostiv Dashboard. What happened?
- Should I use Linux or Windows for best software performance?
- I have connected the probe to my PC or Mac. The Exostiv Probe connect status is still not on. What’s wrong?
- I cannot activate my license online. What now?
- I cannot see the EXOSTIV button in Vivado
- Which OS is supported?
- How do I activate my node-locked license?
- Which date is taken into account for my license subscription?
- Where can I find my license key?
- How do I install the license server for floating licenses?
- Is EXOSTIV Dashboard always backward compatible with an IP generated with an older version?
- How do I update the MICA board configuration?
- Can I run the floating license server as a service?
- Limitations and known issues
-
Bundles and licensing
- How do I set up the Exostiv Dashboard client to lease floating licenses from the server?
- I have a permanent / perpetual license, but I see it has expired. What happened?
- Can I activate the license through a proxy?
- I cannot lease a floating license in Debian 9 / Debian Stretch
- What is the software build number and how can I check it?
- I cannot activate my license online. What now?
- Can I upgrade my Probe?
- How do I activate my node-locked license?
- Which date is taken into account for my license subscription?
- Where can I find my license key?
- What kind of licensing is available?
- How do I install the license server for floating licenses?
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Core Inserter
- In netlist insertion mode, how are nets preserved so they can be probed and not removed during logic optimization?
- Can I use transceivers located in separate quads with the same Exostiv probe?
- Issue when using Vivado 2020.2
- AMD FPGA: which files are produced in RTL flow and how do I use them?
- Intel FPGA: which files are produced in RTL flow and how do I use them?
- Microchip FPGA: which files are produced in RTL flow and how do I use them?
- Which files are produced in RTL flow and how do I use them?
- ‘Failed to assign pinout’ error
- How to use the timing constraints generated by Exostiv Dashboard for Intel?
- My version of Linux does not support libusb. Can I still use the Core Inserter?
- Can I run Vivado and Exostiv Dashboard on separate machines for netlist core insertion?
- What is ‘Number of pipes’ in the Capture Configuration of EXOSTIV IP?
- What is the software build number and how can I check it?
- Can I start Exostiv Dashboard in console mode (TCL)?
- Can I call Exostiv Dashboard from Vivado?
- Exostiv Dashboard Tcl commands list
- What is the ‘event counter’ and how do I use it?
- RTL IP core insertion limitations
- Using ‘Design Checkpoint’ (DCP) flow type
- What are the differences between RTL and netlist flows?
- Which FPGA devices are supported?
- How is EXOSTIV IP set up and generated?
- Which OS is supported?
- How much FPGA resources does Exostiv IP consume?
- How many FPGA nodes can I connect to EXOSTIV IP?
- Can I use Synplify instead of the FPGA vendor synthesis tool?
- Can I probe multiple clock domains?
- Can I use a single EXOSTIV Probe with multiple FPGA devices?
- Does EXOSTIV Dashboard provide design partitioning?
- What is the ‘Vivado link timeout’ setting?
- What is ‘Storage Qualification’?
- I cannot insert EXOSTIV IP because there is an existing instance with the same name in the target design
- Do you provide a scripting interface?
- How can I easily wire my IP throughout hierarchy in RTL flow?
- How do I remove EXOSTIV IP from my netlist to restart insertion?
- Can I share transceiver resources between EXOSTIV IP and the design?
- I need a very specific trigger condition. What can I do?
- Is EXOSTIV Dashboard always backward compatible with an IP generated with an older version?
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EXOSTIV IP
- Microchip FPGA: which files are produced in RTL flow and how do I use them?
- In netlist insertion mode, how are nets preserved so they can be probed and not removed during logic optimization?
- Issue when using Vivado 2020.2
- AMD FPGA: which files are produced in RTL flow and how do I use them?
- Intel FPGA: which files are produced in RTL flow and how do I use them?
- How do Exostiv Blade IP and Exostiv IP compare?
- Can I use transceivers located in separate quads with the same Exostiv probe?
- What is the ‘User Register’ and how do I use it?
- Which files are produced in RTL flow and how do I use them?
- ‘Failed to assign pinout’ error
- How to use the timing constraints generated by Exostiv Dashboard for Intel?
- Can I use optical SFP cables?
- How to prevent Synplify from changing the net names?
- What is ‘Number of pipes’ in the Capture Configuration of EXOSTIV IP?
- How do I send a cross-capture unit trigger?
- What is the ‘event counter’ and how do I use it?
- Can I rename the probed signals?
- RTL IP core insertion limitations
- Using ‘Design Checkpoint’ (DCP) flow type
- Which FPGA devices are supported?
- How is EXOSTIV IP set up and generated?
- How much FPGA resources does Exostiv IP consume?
- How many FPGA nodes can I connect to EXOSTIV IP?
- Can I use Synplify instead of the FPGA vendor synthesis tool?
- Can I probe multiple clock domains?
- Why do I get an ‘overflow’?
- Can the EXOSTIV Probe provide the transceiver clock?
- What is ‘Storage Qualification’?
- EXOSTIV Probe cannot connect to the target design. What now?
- How can I easily wire my IP throughout hierarchy in RTL flow?
- How do I remove EXOSTIV IP from my netlist to restart insertion?
- How many nodes can I sample continuously without creating overflows?
- Can I share transceiver resources between EXOSTIV IP and the design?
- Is EXOSTIV Dashboard always backward compatible with an IP generated with an older version?
- How do I update the MICA board configuration?
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Analyzer
- Myriad v2 interface
- What is the maximum capture length for EXOSTIV?
- How to use libusb without administrator privileges?
- What is the software build number and how can I check it?
- EXOSTIV waves ‘binary format’ description
- Can I export the waves to a non-native format automatically?
- Can I start Exostiv Dashboard in console mode (TCL)?
- How do I send a cross-capture unit trigger?
- Can I call Exostiv Dashboard from Vivado?
- Exostiv Dashboard Tcl commands list
- Can I rename the probed signals?
- Which FPGA devices are supported?
- Which OS is supported?
- What is the difference between ‘Burst to Probe’ and ‘Stream to Probe’?
- Can I probe multiple clock domains?
- Can we export the waves?
- Why do I get an ‘overflow’?
- What is ‘Storage Qualification’?
- Do you provide a scripting interface?
- How do I run multiple capture units simultaneously?
- EXOSTIV Probe cannot connect to the target design. What now?
- How many nodes can I sample continuously without creating overflows?
- I need a very specific trigger condition. What can I do?
- Is EXOSTIV Dashboard always backward compatible with an IP generated with an older version?
-
EXOSTIV Probe
- How do I know if my capture unit is able to stream data?
- Once in a while, the Probe disconnects from the PC. What happened?
- Can I use transceivers located in separate quads with the same Exostiv probe?
- I cannot connect to the probe over USB
- Windows cannot install the driver automatically. What now?
- The front panel LED is blinking on EXOSTIV Probe. What does it mean?
- How do I match transceivers on my board with these on the probe?
- Can I use optical SFP cables?
- Does EXOSTIV support ASIC / SoC prototyping systems?
- Probe firmware update
- What is the maximum capture length for EXOSTIV?
- The application crashes when connecting to the probe or updating the firmware
- I have connected the probe to my PC or Mac. The Exostiv Probe connect status is still not on. What’s wrong?
- What are the switches for on the FMC to HDMI adapter?
- How do I connect the Probe to my board?
- Can I use any HDMI cable with EXOSTIV Probe?
- What is the difference between ‘Burst to Probe’ and ‘Stream to Probe’?
- Can I upgrade my Probe?
- Can I use a single EXOSTIV Probe with multiple FPGA devices?
- Which FPGA boards are supported out of the box?
- Can the EXOSTIV Probe provide the transceiver clock?
- EXOSTIV Probe cannot connect to the target design. What now?
- How many nodes can I sample continuously without creating overflows?
- Where can I find a CE declaration of conformity for EXOSTIV Probe?
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Troubleshooting
- Once in a while, the Probe disconnects from the PC. What happened?
- Known issue: GTH bug can result in CPLL in failure state
- Segmentation fault (core dumped) QT_QPA_PLATFORM_PLUGIN_PATH – crash
- FPGA database update package installation
- Vivado core generation stops unexpectedly
- Can I use transceivers located in separate quads with the same Exostiv probe?
- Issue when using Vivado 2020.2
- Error : 0x80030004
- Error : 0x80030103
- AMD FPGA: which files are produced in RTL flow and how do I use them?
- Intel FPGA: which files are produced in RTL flow and how do I use them?
- Core inserter error – ERROR: [Common 17-165] Too many positional options when parsing
- How do I set up the Exostiv Dashboard client to lease floating licenses from the server?
- How to check the expiration date of my floating license?
- How to check the expiration date of my node-locked license?
- My license is not activated anymore!
- I have a permanent / perpetual license, but I see it has expired. What happened?
- Microchip FPGA: which files are produced in RTL flow and how do I use them?
- How do I know if my capture unit is able to stream data?
- EXOSTIV Dashboard-M – Release Notes
- I received an unexpected overflow error with a burst size smaller than 256 or 512 samples. What happens?
- EXOSTIV Dashboard-A – Release Notes
- EXOSTIV Dashboard-I – Release Notes
- I cannot connect to the probe over USB
- ‘Failed to assign pinout’ error
- Windows cannot install the driver automatically. What now?
- How to use the timing constraints generated by Exostiv Dashboard for Intel?
- My version of Linux does not support libusb. Can I still use the Core Inserter?
- The front panel LED is blinking on EXOSTIV Probe. What does it mean?
- How do I match transceivers on my board with these on the probe?
- Can I run Vivado and Exostiv Dashboard on separate machines for netlist core insertion?
- My keyboard is scrambled in EXOSTIV Dashboard. What happens?
- Can I use optical SFP cables?
- Vivado DRC error – PLDS-1 rule violation encountered. What does this mean?
- How to prevent Synplify from changing the net names?
- Can I activate the license through a proxy?
- I cannot lease a floating license in Debian 9 / Debian Stretch
- How to use libusb without administrator privileges?
- What is ‘Number of pipes’ in the Capture Configuration of EXOSTIV IP?
- Vivado does not start anymore after installing the latest version of Exostiv Dashboard. What happened?
- Should I use Linux or Windows for best software performance?
- Core insertion gets cancelled immediately. What happens?
- Core insertion is cancelled at ‘Starting Vivado Shell’ step
- Exostiv Dashboard cannot link to Vivado. What happens?
- Project file name, directory name and directory permissions
- The application crashes when connecting to the probe or updating the firmware
- I have connected the probe to my PC or Mac. The Exostiv Probe connect status is still not on. What’s wrong?
- I cannot activate my license online. What now?
- I cannot see the EXOSTIV button in Vivado
- What is the ‘Vivado link timeout’ setting?
- EXOSTIV Probe cannot connect to the target design. What now?
- Is EXOSTIV Dashboard always backward compatible with an IP generated with an older version?
- How do I update the MICA board configuration?
- Limitations and known issues
-
Miscellaneous
- How do I know if my capture unit is able to stream data?
- How to check the expiration date of my floating license?
- How to check the expiration date of my node-locked license?
- What is the ‘User Register’ and how do I use it?
- My version of Linux does not support libusb. Can I still use the Core Inserter?
- How do I match transceivers on my board with these on the probe?
- My keyboard is scrambled in EXOSTIV Dashboard. What happens?
- Can I use optical SFP cables?
- Does EXOSTIV support ASIC / SoC prototyping systems?
- How to prevent Synplify from changing the net names?
- Probe firmware update
- Is MacOS supported?
- What is the maximum capture length for EXOSTIV?
- Can I activate the license through a proxy?
- What is the software build number and how can I check it?
- Should I use Linux or Windows for best software performance?
- Can I start Exostiv Dashboard in console mode (TCL)?
- Exostiv Dashboard Tcl commands list
- FPGA-Based Prototyping or ASIC Prototyping?
- I have connected the probe to my PC or Mac. The Exostiv Probe connect status is still not on. What’s wrong?
- Where are the waves stored and can I easily transfer them to a new project?
- What are the switches for on the FMC to HDMI adapter?
- I cannot see the EXOSTIV button in Vivado
- How do I update the MICA board configuration?
- Accessories
- Can I use transceivers located in separate quads with the same Exostiv probe?
- What is the difference between ‘Burst to Probe’ and ‘Stream to Probe’?
- How can I easily wire my IP throughout hierarchy in RTL flow?
